diff options
author | Mary Ruthven <mruthven@chromium.org> | 2021-01-11 11:27:12 -0800 |
---|---|---|
committer | Commit Bot <commit-bot@chromium.org> | 2021-01-11 21:55:20 +0000 |
commit | ec643f0d99397eafa09ab39b2d7dd6b968bd70d8 (patch) | |
tree | 76109b01c5760134d13384678b5ce126e29fba8c /include | |
parent | 17baff2bd51e5b14fa9992f4cddca96742a7dea8 (diff) | |
download | chrome-ec-ec643f0d99397eafa09ab39b2d7dd6b968bd70d8.tar.gz |
coil: cleanup commentsstabilize-rust-13720.B-cr50_stab
BUG=b:175244613
TEST=make buildall -j
Change-Id: Icbd143b072fdd5df3b67d7e5a09ee6c01a77f6b9
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2622889
Reviewed-by: Namyoon Woo <namyoon@chromium.org>
Diffstat (limited to 'include')
-rw-r--r-- | include/config.h | 18 | ||||
-rw-r--r-- | include/spi.h | 2 | ||||
-rw-r--r-- | include/spi_nor.h | 8 | ||||
-rw-r--r-- | include/test_util.h | 4 | ||||
-rw-r--r-- | include/tpm_registers.h | 8 |
5 files changed, 21 insertions, 19 deletions
diff --git a/include/config.h b/include/config.h index 067ba0b9da..d37fd3ea41 100644 --- a/include/config.h +++ b/include/config.h @@ -2590,13 +2590,13 @@ #undef CONFIG_HOSTCMD_ESPI_VW_SLP_S3 #undef CONFIG_HOSTCMD_ESPI_VW_SLP_S4 -/* MCHP next two items are EC eSPI slave configuration */ -/* Maximum clock frequence eSPI EC slave advertises +/* MCHP next two items are EC eSPI peripheral configuration */ +/* Maximum clock frequence eSPI EC peripheral advertises * Values in MHz are 20, 25, 33, 50, and 66 */ #undef CONFIG_HOSTCMD_ESPI_EC_MAX_FREQ -/* EC eSPI slave advertises IO lanes +/* EC eSPI peripheral advertises IO lanes * 0 = Single * 1 = Single and Dual * 2 = Single and Quad @@ -3138,17 +3138,19 @@ */ #undef CONFIG_SPI_NOR_SMART_ERASE -/* SPI master feature */ +/* SPI controller feature */ #undef CONFIG_SPI_CONTROLLER -/* SPI master halfduplex/3-wire mode */ +/* SPI controller halfduplex/3-wire mode */ #undef CONFIG_SPI_HALFDUPLEX -/* SPI master configure gpios on init */ +/* SPI controller configure gpios on init */ #undef CONFIG_SPI_CONTROLLER_CONFIGURE_GPIOS -/* Support SPI masters without GPIO-specified Chip Selects, instead rely on the - * SPI master port's hardwired CS pin. */ +/* + * Support SPI controller's without GPIO-specified Chip Selects, instead rely on + * the SPI controller port's hardwired CS pin. + */ #undef CONFIG_SPI_CONTROLLER_NO_CS_GPIOS /* Support testing SPI periph interface driver. */ diff --git a/include/spi.h b/include/spi.h index c42b7ab757..10286accab 100644 --- a/include/spi.h +++ b/include/spi.h @@ -30,7 +30,7 @@ enum spi_clock_mode { struct spi_device_t { /* * SPI port the device is connected to. - * On some architecture, this is SPI master port index, + * On some architecture, this is SPI controller port index, * on other the SPI port index directly. */ uint8_t port; diff --git a/include/spi_nor.h b/include/spi_nor.h index 173da85012..d56d26802c 100644 --- a/include/spi_nor.h +++ b/include/spi_nor.h @@ -41,7 +41,7 @@ struct spi_nor_device_t { /* Name of the Serial NOR Flash device. */ const char *name; - /* Index of the SPI master which this device is connected through. */ + /* Index of the SPI controller this device is connected through. */ const enum spi_device spi_controller; /* Maximum timeout per command in microseconds. */ @@ -109,9 +109,9 @@ int spi_nor_init(void); * * WARNING: * 1) In 3 Byte addressing mode only 16MiB of Serial NOR Flash is accessible. - * 2) If there's a second SPI master communicating with this Serial NOR Flash - * part on the board, the user is responsible for ensuring addressing mode - * compatibility and cooperation. + * 2) If there's a second SPI controller communicating with this Serial NOR + * Flash part on the board, the user is responsible for ensuring addressing + * mode compatibility and cooperation. * 3) The user must ensure that multiple users do not trample on each other * by having multiple parties changing the device's addressing mode. * diff --git a/include/test_util.h b/include/test_util.h index 21ea21595b..4f98d29a6e 100644 --- a/include/test_util.h +++ b/include/test_util.h @@ -268,7 +268,7 @@ struct test_i2c_write_dev { * * When this function is called, it should either perform the desired * mock functionality, or return EC_ERROR_INVAL to indicate it does - * not respond to the specified port and slave address. + * not respond to the specified port and peripheral address. * * @param routine Function pointer, with the same prototype as i2c_xfer() */ @@ -280,7 +280,7 @@ struct test_i2c_write_dev { /* * Detach an I2C device. Once detached, any read/write command regarding the - * specified port and slave address returns error. + * specified port and peripheral address returns error. * * @param port The port that the detached device is connected to * @param periph_addr The address of the detached device diff --git a/include/tpm_registers.h b/include/tpm_registers.h index d02bc9e276..d35824dfce 100644 --- a/include/tpm_registers.h +++ b/include/tpm_registers.h @@ -5,8 +5,8 @@ /* * This defines the interface functions for TPM SPI Hardware Protocol. The SPI - * master reads or writes between 1 and 64 bytes to a register designated by a - * 24-bit address. There is no provision for error reporting at this level. + * controller reads or writes between 1 and 64 bytes to a register designated by + * a 24-bit address. There is no provision for error reporting at this level. */ #ifndef __CROS_EC_TPM_REGISTERS_H @@ -16,11 +16,11 @@ #include "common.h" -/* The SPI master is writing data into a TPM register. */ +/* The SPI controller is writing data into a TPM register. */ void tpm_register_put(uint32_t regaddr, const uint8_t *data, uint32_t data_size); -/* The SPI master is reading data from a TPM register. */ +/* The SPI controller is reading data from a TPM register. */ void tpm_register_get(uint32_t regaddr, uint8_t *dest, uint32_t data_size); /* Get the current value of the burst size field of the status register. */ |