diff options
author | Randall Spangler <rspangler@chromium.org> | 2011-12-07 18:51:09 +0000 |
---|---|---|
committer | Vincent Palatin <vpalatin@chromium.org> | 2011-12-07 19:10:02 +0000 |
commit | bdf7da5b082f6d18dd27f1e5d8cca0b12154a28c (patch) | |
tree | 6f14312a6cc70d056efc2bede8728c0868266719 /include | |
parent | abe5786058f4b60dc6d30e7d7c964aae850caa1f (diff) | |
download | chrome-ec-bdf7da5b082f6d18dd27f1e5d8cca0b12154a28c.tar.gz |
Initial sources import 1/3
source files mainly done by Randall.
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Change-Id: Iaff83a842b17f3350fb6f2a3f1597ad4c29bd12a
Diffstat (limited to 'include')
-rw-r--r-- | include/adc.h | 35 | ||||
-rw-r--r-- | include/common.h | 35 | ||||
-rw-r--r-- | include/console.h | 41 | ||||
-rw-r--r-- | include/eeprom.h | 35 | ||||
-rw-r--r-- | include/flash.h | 88 | ||||
-rw-r--r-- | include/flash_commands.h | 23 | ||||
-rw-r--r-- | include/gpio.h | 41 | ||||
-rw-r--r-- | include/host_command.h | 19 | ||||
-rw-r--r-- | include/i2c.h | 29 | ||||
-rw-r--r-- | include/keyboard_scan.h | 16 | ||||
-rw-r--r-- | include/lpc.h | 26 | ||||
-rw-r--r-- | include/lpc_commands.h | 133 | ||||
-rw-r--r-- | include/port80.h | 19 | ||||
-rw-r--r-- | include/powerdemo.h | 16 | ||||
-rw-r--r-- | include/pwm.h | 28 | ||||
-rw-r--r-- | include/shared_mem.h | 39 | ||||
-rw-r--r-- | include/system.h | 100 | ||||
-rw-r--r-- | include/temp_sensor.h | 26 | ||||
-rw-r--r-- | include/uart.h | 112 | ||||
-rw-r--r-- | include/vboot.h | 20 | ||||
-rw-r--r-- | include/version.h | 16 | ||||
-rw-r--r-- | include/x86_power.h | 16 |
22 files changed, 913 insertions, 0 deletions
diff --git a/include/adc.h b/include/adc.h new file mode 100644 index 0000000000..1f01f2c08f --- /dev/null +++ b/include/adc.h @@ -0,0 +1,35 @@ +/* Copyright (c) 2011 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* ADC interface for Chrome EC */ + +#ifndef __CROS_EC_ADC_H +#define __CROS_EC_ADC_H + +#include "common.h" + +/* Value returned by adc_read_*() methods if the read failed. */ +#define ADC_READ_ERROR -1 + +/* Minimum and maximum values returned by adc_read(). */ +#define ADC_READ_MIN 0 +#define ADC_READ_MAX 4095 + +/* ADC channels */ +/* TODO: channel mapping is board-specific */ +enum adc_channel { + ADC_CH_POT = 0, +}; + +/* Initializes the module. */ +int adc_init(void); + +/* Reads an ADC channel. Returns the ADC value, or ADC_READ_ERROR if error. */ +int adc_read(enum adc_channel ch); + +/* Returns the internal EC temperature in K, or ADC_READ_ERROR if error. */ +int adc_read_ec_temperature(void); + +#endif /* __CROS_EC_ADC_H */ diff --git a/include/common.h b/include/common.h new file mode 100644 index 0000000000..ceb2bc873f --- /dev/null +++ b/include/common.h @@ -0,0 +1,35 @@ +/* Copyright (c) 2011 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* common.h - Common includes for Chrome EC */ + +#ifndef __CROS_EC_COMMON_H +#define __CROS_EC_COMMON_H + +#include <stdint.h> + +/* List of common error codes that can be returned */ +enum ec_error_list { + /* Success - no error */ + EC_SUCCESS = 0, + /* Unknown error */ + EC_ERROR_UNKNOWN = 1, + /* Function not implemented yet */ + EC_ERROR_UNIMPLEMENTED = 2, + /* Overflow error; too much input provided. */ + EC_ERROR_OVERFLOW = 3, + /* Timeout */ + EC_ERROR_TIMEOUT = 4, + /* Invalid argument */ + EC_ERROR_INVAL = 5, + /* Already in use */ + EC_ERROR_BUSY = 6, + + /* Module-internal error codes may use this range. */ + EC_ERROR_INTERNAL_FIRST = 0x10000, + EC_ERROR_INTERNAL_LAST = 0x1FFFF +}; + +#endif /* __CROS_EC_COMMON_H */ diff --git a/include/console.h b/include/console.h new file mode 100644 index 0000000000..f8f76860da --- /dev/null +++ b/include/console.h @@ -0,0 +1,41 @@ +/* Copyright (c) 2011 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* console.h - Debug console for Chrome EC */ + +#ifndef __CROS_EC_CONSOLE_H +#define __CROS_EC_CONSOLE_H + +#include "common.h" + +/* Console command */ +struct console_command { + /* Command name. Case-insensitive. */ + const char *name; + /* Handler for the command. argv[0] will be the command name. */ + int (*handler)(int argc, char **argv); +}; + + +/* Console command group */ +struct console_group { + const char *group_name; /* Name of the command group */ + const struct console_command *commands; /* List of commands */ + int command_count; /* Number of commands in list */ +}; + + +/* Initializes the console module. */ +int console_init(void); + + +/* Called by UART when a line of input is pending. */ +void console_has_input(void); + + +/* Registers a group of console commands. */ +int console_register_commands(const struct console_group *group); + +#endif /* __CROS_EC_CONSOLE_H */ diff --git a/include/eeprom.h b/include/eeprom.h new file mode 100644 index 0000000000..70290e17d4 --- /dev/null +++ b/include/eeprom.h @@ -0,0 +1,35 @@ +/* Copyright (c) 2011 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* EEPROM module for Chrome EC */ + +#ifndef __CROS_EC_EEPROM_H +#define __CROS_EC_EEPROM_H + +#include "common.h" + +/* Initializes the module. */ +int eeprom_init(void); + +/* Returns the number of EEPROM blocks on the system. */ +int eeprom_get_block_count(void); + +/* Returns the EEPROM block size in bytes. */ +int eeprom_get_block_size(void); + +/* Reads <size> bytes of data from <offset> in <block> of EEPROM. Offset + * and size must be a multiple of 32 bits. */ +int eeprom_read(int block, int offset, int size, char *data); + +/* Writes <size> bytes of data to <offset> in <block> of EEPROM. Offset + * and size must be a multiple of 32 bits. */ +int eeprom_write(int block, int offset, int size, const char *data); + +/* Hides an EEPROM block until the next reset. */ +int eeprom_hide(int block); + +/* TODO: write protect */ + +#endif /* __CROS_EC_EEPROM_H */ diff --git a/include/flash.h b/include/flash.h new file mode 100644 index 0000000000..38944e43cb --- /dev/null +++ b/include/flash.h @@ -0,0 +1,88 @@ +/* Copyright (c) 2011 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* Flash memory module for Chrome EC */ + +#ifndef __CROS_EC_FLASH_H +#define __CROS_EC_FLASH_H + +#include "common.h" + + +#define FLASH_WRITE_BYTES 4 +#define FLASH_FWB_WORDS 32 +#define FLASH_FWB_BYTES (FLASH_FWB_WORDS * 4) +#define FLASH_ERASE_BYTES 1024 +#define FLASH_PROTECT_BYTES 2048 + + +/* Initializes the module. */ +int flash_init(void); + +/* Returns the usable size of flash in bytes. Note that this is + * smaller than the actual flash size, */ +int flash_get_size(void); + +/* Returns the write / erase / protect block size, in bytes. + * Operations must be aligned to and multiples of the granularity. + * For example, erase operations must have offset and size which are + * multiples of the erase block size. */ +int flash_get_write_block_size(void); +int flash_get_erase_block_size(void); +int flash_get_protect_block_size(void); + +/* Reads <size> bytes of data from offset <offset> into <data>. */ +int flash_read(int offset, int size, char *data); + +/* Writes <size> bytes of data to flash at byte offset <offset>. + * <data> must be 32-bit aligned. */ +int flash_write(int offset, int size, const char *data); + +/* Erases <size> bytes of flash at byte offset <offset>. */ +int flash_erase(int offset, int size); + +/* TODO: not super happy about the following APIs yet. + * + * The theory of operation is that we'll use the last page of flash to + * hold the write protect range, and the flag for whether the last + * page itself should be protected. Then when flash_init() is called, + * it checks if the write protect pin is asserted, and if so, it + * writes (but does not commit) the flash protection registers. + * + * This simulates what a SPI flash does, where the status register + * holds the write protect range, and a bit which protects the status + * register itself. The bit is only obeyed if the write protect pin + * is enabled. + * + * It's an imperfect simulation, because in a SPI flash, as soon as + * you deassert the pin you can alter the status register, where here + * it'll take a cold boot to clear protection. Also, here protection + * gets written to the registers as soon as you set the write protect + * lock, which is different than SPI, where it's effective as soon as + * you set the write protect range. */ + +/* Gets or sets the write protect range in bytes. This setting is + * stored in flash, and persists across reboots. If size is non-zero, + * the write protect range is also locked, and may not be subsequently + * altered until after a cold boot with the write protect pin + * deasserted. */ +int flash_get_write_protect_range(int *offset, int *size); +int flash_set_write_protect_range(int offset, int size); + +/* The write protect range has been stored into the chip registers + * this boot. The flash is write protected and the range cannot be + * changed without rebooting. */ +#define EC_FLASH_WP_RANGE_LOCKED 0x01 +/* The write protect pin was asserted at init time. */ +#define EC_FLASH_WP_PIN_ASSERTED_AT_INIT 0x02 +/* The write protect pin is asserted now. */ +#define EC_FLASH_WP_PIN_ASSERTED_NOW 0x04 + +/* Returns the current write protect status; see EC_FLASH_WP_* + * for valid flags. */ +int flash_get_write_protect_status(void); + + +#endif /* __CROS_EC_FLASH_H */ diff --git a/include/flash_commands.h b/include/flash_commands.h new file mode 100644 index 0000000000..e74fef1318 --- /dev/null +++ b/include/flash_commands.h @@ -0,0 +1,23 @@ +/* Copyright (c) 2011 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* Flash memory commands for Chrome EC */ + +#ifndef __CROS_EC_FLASH_COMMANDS_H +#define __CROS_EC_FLASH_COMMANDS_H + +#include "common.h" +#include "lpc_commands.h" + +/* Initializes the module. */ +int flash_commands_init(void); + +/* Host command handlers. */ +enum lpc_status flash_command_get_info(uint8_t *data); +enum lpc_status flash_command_read(uint8_t *data); +enum lpc_status flash_command_write(uint8_t *data); +enum lpc_status flash_command_erase(uint8_t *data); + +#endif /* __CROS_EC_FLASH_COMMANDS_H */ diff --git a/include/gpio.h b/include/gpio.h new file mode 100644 index 0000000000..05123c4eb6 --- /dev/null +++ b/include/gpio.h @@ -0,0 +1,41 @@ +/* Copyright (c) 2011 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* GPIO module for Chrome EC */ + +#ifndef __CROS_EC_GPIO_H +#define __CROS_EC_GPIO_H + +#include "common.h" + +/* GPIO signal definitions. */ +enum gpio_signal { + /* Firmware write protect */ + EC_GPIO_WRITE_PROTECT = 0, + /* Recovery switch */ + EC_GPIO_RECOVERY_SWITCH, + /* Debug LED */ + EC_GPIO_DEBUG_LED +}; + + +/* Pre-initializes the module. This occurs before clocks or tasks are + * set up. */ +int gpio_pre_init(void); + +/* Initializes the GPIO module. */ +int gpio_init(void); + +/* Functions should return an error if the requested signal is not + * supported / not present on the board. */ + +/* Gets the current value of a signal (0=low, 1=hi). */ +int gpio_get(enum gpio_signal signal, int *value_ptr); + +/* Sets the current value of a signal. Returns error if the signal is + * not supported or is an input signal. */ +int gpio_set(enum gpio_signal signal, int value); + +#endif /* __CROS_EC_GPIO_H */ diff --git a/include/host_command.h b/include/host_command.h new file mode 100644 index 0000000000..fc39683c06 --- /dev/null +++ b/include/host_command.h @@ -0,0 +1,19 @@ +/* Copyright (c) 2011 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* Host command module for Chrome EC */ + +#ifndef __CROS_EC_HOST_COMMAND_H +#define __CROS_EC_HOST_COMMAND_H + +#include "common.h" + +/* Initializes the module. */ +int host_command_init(void); + +/* Called by LPC module when a command is written to port 66h. */ +void host_command_received(int command); + +#endif /* __CROS_EC_HOST_COMMAND_H */ diff --git a/include/i2c.h b/include/i2c.h new file mode 100644 index 0000000000..34076b1f34 --- /dev/null +++ b/include/i2c.h @@ -0,0 +1,29 @@ +/* Copyright (c) 2011 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* I2C interface for Chrome EC */ + +#ifndef __CROS_EC_I2C_H +#define __CROS_EC_I2C_H + +#include "common.h" + +/* Flags for slave address field, in addition to the 8-bit address */ +#define I2C_FLAG_BIG_ENDIAN 0x100 /* 16 byte values are MSB-first */ + +/* Initializes the module. */ +int i2c_init(void); + +/* Reads a 16-bit register from the slave at 8-bit slave address + * <slaveaddr>, at the specified 8-bit <offset> in the slave's address + * space. */ +int i2c_read16(int port, int slave_addr, int offset, int* data); + +/* Writes a 16-bit register to the slave at 8-bit slave address + * <slaveaddr>, at the specified 8-bit <offset> in the slave's address + * space. */ +int i2c_write16(int port, int slave_addr, int offset, int data); + +#endif /* __CROS_EC_I2C_H */ diff --git a/include/keyboard_scan.h b/include/keyboard_scan.h new file mode 100644 index 0000000000..8bc10c2c17 --- /dev/null +++ b/include/keyboard_scan.h @@ -0,0 +1,16 @@ +/* Copyright (c) 2011 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* Keyboard scanner module for Chrome EC */ + +#ifndef __CROS_EC_KEYBOARD_SCAN_H +#define __CROS_EC_KEYBOARD_SCAN_H + +#include "common.h" + +/* Initializes the module. */ +int keyboard_scan_init(void); + +#endif /* __CROS_KEYBOARD_SCAN_H */ diff --git a/include/lpc.h b/include/lpc.h new file mode 100644 index 0000000000..ac0b56c137 --- /dev/null +++ b/include/lpc.h @@ -0,0 +1,26 @@ +/* Copyright (c) 2011 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* LPC module for Chrome EC */ + +#ifndef __CROS_EC_LPC_H +#define __CROS_EC_LPC_H + +#include "common.h" + +/* Initializes the LPC module. */ +int lpc_init(void); + +/* Returns a pointer to the host command data buffer. This buffer + * must only be accessed between a notification to + * host_command_received() and a subsequent call to + * lpc_SendHostResponse(). */ +volatile uint8_t *lpc_get_host_range(void); + +/* Sends a response to a host command. The bottom 4 bits of <status> + * are sent in the status byte. */ +void lpc_send_host_response(int status); + +#endif /* __CROS_EC_LPC_H */ diff --git a/include/lpc_commands.h b/include/lpc_commands.h new file mode 100644 index 0000000000..4923db4adb --- /dev/null +++ b/include/lpc_commands.h @@ -0,0 +1,133 @@ +/* Copyright (c) 2011 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* LPC command constants for Chrome EC */ + +#ifndef __CROS_EC_LPC_COMMANDS_H +#define __CROS_EC_LPC_COMMANDS_H + +#include <stdint.h> + +/* LPC command status byte masks */ +/* EC is busy processing a command. This covers both bit 0x04, which + * is the busy-bit, and 0x02, which is the bit which indicates the + * host has written a byte but the EC hasn't picked it up yet. */ +#define EC_LPC_BUSY_MASK 0x06 +#define EC_LPC_STATUS_MASK 0xF0 /* Mask for status codes in status byte */ +#define EC_LPC_GET_STATUS(x) (((x) & EC_LPC_STATUS_MASK) >> 4) + +/* LPC command response codes */ +enum lpc_status { + EC_LPC_STATUS_SUCCESS = 0, + EC_LPC_STATUS_INVALID_COMMAND = 1, + EC_LPC_STATUS_ERROR = 2, + EC_LPC_STATUS_INVALID_PARAM = 3, +}; + + +/* Notes on commands: + * + * Each command is an 8-byte command value. Commands which take + * params or return response data specify structs for that data. If + * no struct is specified, the command does not input or output data, + * respectively. */ + +/* Reboot. This command will work even when the EC LPC interface is + * busy, because the reboot command is processed at interrupt + * level. Note that when the EC reboots, the host will reboot too, so + * there is no response to this command. */ +#define EC_LPC_COMMAND_REBOOT 0xD1 /* Think "die" */ + + +/* Hello. This is a simple command to test the EC is responsive to + * commands. */ +#define EC_LPC_COMMAND_HELLO 0x01 +struct lpc_params_hello { + uint32_t in_data; /* Pass anything here */ +} __attribute__ ((packed)); +struct lpc_response_hello { + uint32_t out_data; /* Output will be in_data + 0x01020304 */ +} __attribute__ ((packed)); + + +/* Get version number */ +#define EC_LPC_COMMAND_GET_VERSION 0x02 +enum lpc_current_image { + EC_LPC_IMAGE_UNKNOWN = 0, + EC_LPC_IMAGE_RO, + EC_LPC_IMAGE_RW_A, + EC_LPC_IMAGE_RW_B +}; +struct lpc_response_get_version { + /* Null-terminated version strings for RO, RW-A, RW-B */ + char version_string_ro[32]; + char version_string_rw_a[32]; + char version_string_rw_b[32]; + uint32_t current_image; /* One of lpc_current_image */ +} __attribute__ ((packed)); + + +/* Read test */ +#define EC_LPC_COMMAND_READ_TEST 0x03 +struct lpc_params_read_test { + uint32_t offset; /* Starting value for read buffer */ + uint32_t size; /* Size to read in bytes */ +} __attribute__ ((packed)); +struct lpc_response_read_test { + uint32_t data[32]; +} __attribute__ ((packed)); + +/*****************************************************************************/ +/* Flash commands */ + +/* Maximum bytes that can be read/written in a single command */ +#define EC_LPC_FLASH_SIZE_MAX 128 + +/* Get flash info */ +#define EC_LPC_COMMAND_FLASH_INFO 0x10 +struct lpc_response_flash_info { + /* Usable flash size, in bytes */ + uint32_t flash_size; + /* Write block size. Write offset and size must be a multiple + * of this. */ + uint32_t write_block_size; + /* Erase block size. Erase offset and size must be a multiple + * of this. */ + uint32_t erase_block_size; + /* Protection block size. Protection offset and size must be a + * multiple of this. */ + uint32_t protect_block_size; +} __attribute__ ((packed)); + + +/* Read flash */ +#define EC_LPC_COMMAND_FLASH_READ 0x11 +struct lpc_params_flash_read { + uint32_t offset; /* Byte offset to read */ + uint32_t size; /* Size to read in bytes */ +} __attribute__ ((packed)); +struct lpc_response_flash_read { + uint8_t data[EC_LPC_FLASH_SIZE_MAX]; +} __attribute__ ((packed)); + + +/* Write flash */ +#define EC_LPC_COMMAND_FLASH_WRITE 0x12 +struct lpc_params_flash_write { + uint32_t offset; /* Byte offset to erase */ + uint32_t size; /* Size to erase in bytes */ + uint8_t data[EC_LPC_FLASH_SIZE_MAX]; +} __attribute__ ((packed)); + + +/* Erase flash */ +#define EC_LPC_COMMAND_FLASH_ERASE 0x13 +struct lpc_params_flash_erase { + uint32_t offset; /* Byte offset to erase */ + uint32_t size; /* Size to erase in bytes */ +} __attribute__ ((packed)); + + +#endif /* __CROS_EC_LPC_COMMANDS_H */ diff --git a/include/port80.h b/include/port80.h new file mode 100644 index 0000000000..060ee7bbd8 --- /dev/null +++ b/include/port80.h @@ -0,0 +1,19 @@ +/* Copyright (c) 2011 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* Port 80 module for Chrome EC */ + +#ifndef __CROS_EC_PORT80_H +#define __CROS_EC_PORT80_H + +#include "common.h" + +/* Initializes the module. */ +int port_80_init(void); + +/* Called by LPC module when a byte of data is written to port 80. */ +void port_80_write(int data); + +#endif /* __CROS_EC_PORT80_H */ diff --git a/include/powerdemo.h b/include/powerdemo.h new file mode 100644 index 0000000000..78acfc095b --- /dev/null +++ b/include/powerdemo.h @@ -0,0 +1,16 @@ +/* Copyright (c) 2011 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* Power state machine demo module for Chrome EC */ + +#ifndef __CROS_EC_POWERDEMO_H +#define __CROS_EC_POWERDEMO_H + +#include "common.h" + +/* Initializes the module. */ +int power_demo_init(void); + +#endif /* __CROS_EC_POWERDEMO_H */ diff --git a/include/pwm.h b/include/pwm.h new file mode 100644 index 0000000000..50534f2434 --- /dev/null +++ b/include/pwm.h @@ -0,0 +1,28 @@ +/* Copyright (c) 2011 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* PWM module for Chrome EC */ + +#ifndef __CROS_EC_PWM_H +#define __CROS_EC_PWM_H + +#include "common.h" + +/* Initializes the module. */ +int pwm_init(void); + +/* Gets the current fan RPM. */ +int pwm_get_fan_rpm(void); + +/* Sets the target fan RPM. Pass -1 to set fan to maximum. */ +int pwm_set_fan_target_rpm(int rpm); + +/* Sets the keyboard backlight percentage (0=off, 100=max). */ +int pwm_set_keyboard_backlight(int percent); + +/* Sets the power LED brightness to the specified percent (0=off, 100=max). */ +int pwm_set_power_led(int percent); + +#endif /* __CROS_EC_PWM_H */ diff --git a/include/shared_mem.h b/include/shared_mem.h new file mode 100644 index 0000000000..14b6613a9a --- /dev/null +++ b/include/shared_mem.h @@ -0,0 +1,39 @@ +/* Copyright (c) 2011 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* Shared memory interface for Chrome EC. + * + * This is intended to supply a relatively large block of memory for + * use by a task for a relatively short amount of time. For example, + * verified boot may need a buffer to hold signature data during a + * verification operation. It is NOT intended for allocating + * long-term buffers; those should in general be static variables + * allocated at compile-time. It is NOT a full-featured replacement + * for malloc() / free(). */ + +#ifndef __CROS_EC_SHARED_MEM_H +#define __CROS_EC_SHARED_MEM_H + +#include "common.h" + +/* Initializes the module. */ +int shared_mem_init(void); + +/* Returns the maximum amount of shared memory which can be acquired, + * in bytes. */ +int shared_mem_size(void); + +/* Acquires a shared memory area of the requested size in bytes. If + * wait != 0, will wait for the area to be available; if wait == 0, + * will fail with EC_ERROR_BUSY if the request cannot be fulfilled + * immediately. On success, sets *dest_ptr to the start of the memory + * area and returns EC_SUCCESS. */ +int shared_mem_acquire(int size, int wait, char **dest_ptr); + +/* Releases a shared memory area previously allocated via + * shared_mem_acquire(). */ +void shared_mem_release(void *ptr); + +#endif /* __CROS_EC_SHARED_MEM_H */ diff --git a/include/system.h b/include/system.h new file mode 100644 index 0000000000..46cb5bf730 --- /dev/null +++ b/include/system.h @@ -0,0 +1,100 @@ +/* Copyright (c) 2011 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* System module for Chrome EC */ + +#ifndef __CROS_EC_SYSTEM_H +#define __CROS_EC_SYSTEM_H + +#include "common.h" + +/* Reset causes */ +enum system_reset_cause_t { + /* Unknown reset cause */ + SYSTEM_RESET_UNKNOWN = 0, + /* System reset cause is known, but not one of the causes + * listed below */ + SYSTEM_RESET_OTHER, + /* Brownout */ + SYSTEM_RESET_BROWNOUT, + /* Power-on reset */ + SYSTEM_RESET_POWER_ON, + /* Reset caused by asserting reset (RST#) pin */ + SYSTEM_RESET_RESET_PIN, + /* Software requested cold reset */ + SYSTEM_RESET_SOFT_COLD, + /* Software requested warm reset */ + SYSTEM_RESET_SOFT_WARM, + /* Watchdog timer reset */ + SYSTEM_RESET_WATCHDOG, + /* the RTC alarm triggered power on */ + SYSTEM_RESET_RTC_ALARM, + /* the Wake pin triggered power on */ + SYSTEM_RESET_WAKE_PIN, + /* the low battery detection triggered power on */ + SYSTEM_RESET_LOW_BATTERY, +}; + +/* System images */ +enum system_image_copy_t { + SYSTEM_IMAGE_UNKNOWN = 0, + SYSTEM_IMAGE_RO, + SYSTEM_IMAGE_RW_A, + SYSTEM_IMAGE_RW_B +}; + +/* Pre-initializes the module. This occurs before clocks or tasks are + * set up. */ +int system_pre_init(void); + +/* Initializes the system module. */ +int system_init(void); + +/* Returns the cause of the last reset, or SYSTEM_RESET_UNKNOWN if + * the cause is not known. */ +enum system_reset_cause_t system_get_reset_cause(void); + +/* Returns a text description of the last reset cause. */ +const char *system_get_reset_cause_string(void); + +/* Returns the image copy which is currently running. */ +enum system_image_copy_t system_get_image_copy(void); + +/* Returns a text description of the image copy which is currently running. */ +const char *system_get_image_copy_string(void); + +/* Jumps to the specified image copy. Only works from RO firmware. */ +int system_run_image_copy(enum system_image_copy_t copy); + +/* Returns the version string for an image copy, or an empty string if + * error. If copy==SYSTEM_IMAGE_UNKNOWN, returns the version for the + * currently-running image. */ +const char *system_get_version(enum system_image_copy_t copy); + +/* Resets the system. If is_cold!=0, performs a cold reset (which + * resets on-chip peripherals); else performs a warm reset (which does + * not reset on-chip peripherals). If successful, does not return. + * Returns error if the reboot type cannot be requested (e.g. brownout + * or reset pin). */ +int system_reset(int is_cold); + +/* Sets a scratchpad register to the specified value. The scratchpad + * register must maintain its contents across a software-requested + * warm reset. */ +int system_set_scratchpad(uint32_t value); + +/* Returns the current scratchpad register value. */ +uint32_t system_get_scratchpad(void); + +/* TODO: request sleep. How do we want to handle transitioning + * to/from low-power states? */ + +/* put the system in hibernation for the specified duration */ +void system_hibernate(uint32_t seconds, uint32_t microseconds); + +/* minimum duration to get proper hibernation */ +#define SYSTEM_HIB_MINIMUM_DURATION 0, 1000 + +#endif /* __CROS_EC_SYSTEM_H */ diff --git a/include/temp_sensor.h b/include/temp_sensor.h new file mode 100644 index 0000000000..863f9d7d51 --- /dev/null +++ b/include/temp_sensor.h @@ -0,0 +1,26 @@ +/* Copyright (c) 2011 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* Temperature sensor module for Chrome EC */ + +#ifndef __CROS_EC_TEMP_SENSOR_H +#define __CROS_EC_TEMP_SENSOR_H + +#include "common.h" + +enum temp_sensor_id { + TEMP_SENSOR_CASE = 0, /* Case temperature */ + TEMP_SENSOR_CASE_DIE, /* Case temperature sensor die */ + TEMP_SENSOR_EC_INTERNAL, /* EC internal temperature sensor */ +}; + +/* Initializes the module. */ +int temp_sensor_init(void); + +/* Returns the most recently measured temperature for the sensor in K, + * or -1 if error. */ +int temp_sensor_read(enum temp_sensor_id id); + +#endif /* __CROS_EC_TEMP_SENSOR_H */ diff --git a/include/uart.h b/include/uart.h new file mode 100644 index 0000000000..12ecf7a1a6 --- /dev/null +++ b/include/uart.h @@ -0,0 +1,112 @@ +/* Copyright (c) 2011 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* uart.h - UART module for Chrome EC */ + +#ifndef __CROS_EC_UART_H +#define __CROS_EC_UART_H + +#include "common.h" + + +/* Initializes the UART module. */ +int uart_init(void); + + +/* Enables console mode if <enable>!=0. In console mode: + * - Input is echoed + * - Input CRLF and CR are translated to LF + * - Input backspace will remove characters from the input buffer (which + * is pretty much only useful if the input handler is only triggered on + * newline) + * - Output LF is translated to CRLF */ +void uart_set_console_mode(int enable); + +/*****************************************************************************/ +/* Output functions + * + * Output is buffered. If the buffer overflows, subsequent output is + * discarded. */ + +/* Put a null-terminated string to the UART, like fputs(). + * + * Returns error if output was truncated. */ +int uart_puts(const char *outstr); + +/* Print formatted output to the UART, like printf(). + * + * Returns error if output was truncated. + * + * Must support format strings for: + * char (%c) + * string (%s) + * native int (signed/unsigned) (%d / %u / %x) + * int32_t / uint32_t (%d / %x) + * int64_t / uint64_t (%ld / %lu / %lx) + * pointer (%p) + * including padding (%-5s, %8d, %08x) + * + * Note: Floating point output (%f / %g) is not required. + */ +int uart_printf(const char *format, ...); + +/* Flushes output. Blocks until UART has transmitted all output. */ +void uart_flush_output(void); + +/* Flushes output. + * + * Blocks until UART has transmitted all output, + * even if we are in high priority interrupt context + */ +void uart_emergency_flush(void); + +/*****************************************************************************/ +/* Input functions + * + * Input is buffered. If the buffer overflows, the oldest input in + * the buffer is discarded to make room for the new input. + * + * Input lines may be terminated by CR ('\r'), LF ('\n'), or CRLF; all + * are translated to newline. */ + +/* Flushes input buffer, discarding all input. */ +void uart_flush_input(void); + +/* Non-destructively checks for a character in the input buffer. + * + * Returns the offset into the input buffer of character <c>, or -1 if + * it is not in the input buffer. */ +int uart_peek(int c); + +/* Reads a single character of input, similar to fgetc(). Returns the + * character, or -1 if no input waiting. */ +int uart_getc(void); + +/* Reads characters from the UART, similar to fgets(). + * + * Reads input until one of the following conditions is met: + * (1) <size-1> characters have been read. + * (2) A newline ('\n') has been read. + * (3) The input buffer is empty. + * + * Condition (3) means this call never blocks. This is important + * because it prevents a race condition where the caller calls + * UartPeek() to see if input is waiting, or is notified by the + * callack that input is waiting, but then the input buffer overflows + * or someone else grabs the input before UartGets() is called. + * + * Characters are stored in <dest> and are null-terminated. + * Characters include the newline if present, so that the caller can + * distinguish between a complete line and a truncated one. If the + * input buffer is empty, a null-terminated empty string ("") is + * returned. + * + * Returns the number of characters read (not counting the terminating + * null). */ +int uart_gets(char *dest, int size); + +/* TODO: getc(), putc() equivalents? */ + +#endif /* __CROS_EC_UART_H */ diff --git a/include/vboot.h b/include/vboot.h new file mode 100644 index 0000000000..430c617a52 --- /dev/null +++ b/include/vboot.h @@ -0,0 +1,20 @@ +/* Copyright (c) 2011 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* Verified boot module for Chrome EC */ + +#ifndef __CROS_EC_VBOOT_H +#define __CROS_EC_VBOOT_H + +#include "common.h" + +/* Pre-initializes the module. This occurs before clocks or tasks are + * set up. */ +int vboot_pre_init(void); + +/* Initializes the module. */ +int vboot_init(void); + +#endif /* __CROS_EC_VBOOT_H */ diff --git a/include/version.h b/include/version.h new file mode 100644 index 0000000000..0031339c34 --- /dev/null +++ b/include/version.h @@ -0,0 +1,16 @@ +/* Copyright (c) 2011 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* Version number for Chrome EC */ + +#ifndef __CROS_EC_VERSION_H +#define __CROS_EC_VERSION_H + +#define CROS_EC_VERSION_MAJOR 0 +#define CROS_EC_VERSION_MINOR 1 +#define CROS_EC_VERSION_SUBMINOR 2 +#define CROS_EC_VERSION_STRING "Link.0.1.2" + +#endif /* __CROS_EC_VERSION_H */ diff --git a/include/x86_power.h b/include/x86_power.h new file mode 100644 index 0000000000..3343b237e2 --- /dev/null +++ b/include/x86_power.h @@ -0,0 +1,16 @@ +/* Copyright (c) 2011 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +/* x86 power module for Chrome EC */ + +#ifndef __CROS_EC_X86_POWER_H +#define __CROS_EC_X86_POWER_H + +#include "common.h" + +/* Initializes the module. */ +int x86_power_init(void); + +#endif /* __CROS_EC_X86_POWER_H */ |