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| author | Patryk Duda <pdk@semihalf.com> | 2021-08-23 14:21:08 +0200 |
|---|---|---|
| committer | Chromeos LUCI <chromeos-scoped@luci-project-accounts.iam.gserviceaccount.com> | 2022-03-28 18:17:10 +0000 |
| commit | cf96131c91213628e56ed82527b83d20177609bf (patch) | |
| tree | aea9b8bfb672e86cd654deebe442e9cd2bac7a36 /include/panic.h | |
| parent | d1d2aeb01fda2c069c7cdb543b5e0fbcbe755613 (diff) | |
| download | chrome-ec-cf96131c91213628e56ed82527b83d20177609bf.tar.gz | |
cortex-m/panic: Introduce CONFIG_PANIC_STRIP_GPR option
If set, this option will prevent saving General Purpose Registers
during panic. When software panic occurs, R4 and R5 will be saved,
because they contain additional information about panic.
This should be enabled on boards which are processing sensitive data
and panic could cause the leak.
BUG=b:218982018,b:193408648
BRANCH=none
TEST=Trigger panic using 'crash' command. After reboot use 'panicinfo'
to check what was saved. When CPU exception occurred registers
R0-R12 should be set to 0. In case of software panic, R4 and R5 can
contain panic reason and additional information.
Signed-off-by: Patryk Duda <pdk@semihalf.com>
Change-Id: I06f9c4bb07f936f0822f70a05e19c8d99c68abfb
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3114645
Commit-Queue: Marcin Wojtas <mwojtas@google.com>
Reviewed-by: Craig Hesling <hesling@chromium.org>
Reviewed-by: Tom Hughes <tomhughes@chromium.org>
(cherry picked from commit 0bb062c8cd7c201571da60edd828c007dcbc436c)
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3508419
Reviewed-by: Patryk Duda <patrykd@google.com>
Diffstat (limited to 'include/panic.h')
| -rw-r--r-- | include/panic.h | 38 |
1 files changed, 33 insertions, 5 deletions
diff --git a/include/panic.h b/include/panic.h index 1984081dd7..159204653c 100644 --- a/include/panic.h +++ b/include/panic.h @@ -17,13 +17,41 @@ extern "C" { #endif +enum cortex_panic_frame_registers { + CORTEX_PANIC_FRAME_REGISTER_R0 = 0, + CORTEX_PANIC_FRAME_REGISTER_R1, + CORTEX_PANIC_FRAME_REGISTER_R2, + CORTEX_PANIC_FRAME_REGISTER_R3, + CORTEX_PANIC_FRAME_REGISTER_R12, + CORTEX_PANIC_FRAME_REGISTER_LR, + CORTEX_PANIC_FRAME_REGISTER_PC, + CORTEX_PANIC_FRAME_REGISTER_PSR, + NUM_CORTEX_PANIC_FRAME_REGISTERS +}; + +enum cortex_panic_registers { + CORTEX_PANIC_REGISTER_PSP = 0, + CORTEX_PANIC_REGISTER_IPSR, + CORTEX_PANIC_REGISTER_MSP, + CORTEX_PANIC_REGISTER_R4, + CORTEX_PANIC_REGISTER_R5, + CORTEX_PANIC_REGISTER_R6, + CORTEX_PANIC_REGISTER_R7, + CORTEX_PANIC_REGISTER_R8, + CORTEX_PANIC_REGISTER_R9, + CORTEX_PANIC_REGISTER_R10, + CORTEX_PANIC_REGISTER_R11, + CORTEX_PANIC_REGISTER_LR, + NUM_CORTEX_PANIC_REGISTERS +}; + /* ARM Cortex-Mx registers saved on panic */ struct cortex_panic_data { - uint32_t regs[12]; /* psp, ipsr, msp, r4-r11, lr(=exc_return). - * In version 1, that was uint32_t regs[11] = - * psp, ipsr, lr, r4-r11 - */ - uint32_t frame[8]; /* r0-r3, r12, lr, pc, xPSR */ + /* See cortex_panic_registers enum for information about registers */ + uint32_t regs[NUM_CORTEX_PANIC_REGISTERS]; + + /* See cortex_panic_frame_registers enum for more information */ + uint32_t frame[NUM_CORTEX_PANIC_FRAME_REGISTERS]; uint32_t mmfs; uint32_t bfar; |