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| author | Randall Spangler <rspangler@chromium.org> | 2012-05-29 16:53:05 -0700 |
|---|---|---|
| committer | Randall Spangler <rspangler@chromium.org> | 2012-05-30 13:12:34 -0700 |
| commit | 858d87cfaae5182b1d6cf008a7e33766612ab000 (patch) | |
| tree | ad49348fae3e76b587b4446cbb9af01f70386697 /include/console.h | |
| parent | 6654374f31f562dfd0012f83ca4d58735458e4b2 (diff) | |
| download | chrome-ec-858d87cfaae5182b1d6cf008a7e33766612ab000.tar.gz | |
Add basic SPI support to link
This adds SPI transaction support, and a debug command to read a few
values from the SPI EEPROM.
Note that the SPI controller is normally *disabled* with all its I/Os
high-Z, so this will not interfere with main processor or Servo on the
SPI bus. The bus is only enabled during the SPIROM command itself.
BUG=chrome-os-partner:7844
TEST=manual
1) Reboot system
2) on EC console, 'spirom'. Should print
Man/Dev ID : 0xef 0x16
JEDEC ID : 0xef 0x40 0x17
Unique ID : 0xd1 0x61 0x44 0xb0 0x63 0x5d 0x40 0x32
Status reg 1: 0x00
Status reg 2: 0x00
Note that unique ID is, well, unique, so it won't match my value. But
it should still be something not all 0xff's.
3) Power on the system. x86 should still boot normally, indicating
that the EC isn't interfering with the SPI bus.
Change-Id: I53bf5fdbbe7a37949375d0463e30e408cc6fb6a8
Diffstat (limited to 'include/console.h')
| -rw-r--r-- | include/console.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/include/console.h b/include/console.h index 3ad4150fe4..f0d131249d 100644 --- a/include/console.h +++ b/include/console.h @@ -44,6 +44,7 @@ enum console_channel { CC_PORT80, CC_POWERBTN, CC_PWM, + CC_SPI, CC_SYSTEM, CC_TASK, CC_USBCHARGE, |