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authorShawn Nematbakhsh <shawnn@chromium.org>2015-09-04 19:09:33 -0700
committerchrome-bot <chrome-bot@chromium.org>2015-09-16 14:49:31 -0700
commitd58e54730c03290296df5bb65cb84264e4b2facc (patch)
treed736570c84a0e9737b8881ec68b073327a5c2ae5 /include/config_std_internal_flash.h
parent4b3c13ddfefd229dde49fb4cbf5a6bfc49f64973 (diff)
downloadchrome-ec-d58e54730c03290296df5bb65cb84264e4b2facc.tar.gz
cleanup: Rename geometry constants
Rename and add geometry constants to match spec doc - https://goo.gl/fnzTvr. CONFIG_FLASH_BASE becomes CONFIG_PROGRAM_MEMORY_BASE CONFIG_FLASH_MAPPED becomes CONFIG_MAPPED_STORAGE Add CONFIG_INTERNAL_STORAGE, CONFIG_EXTERNAL_STORAGE and CONFIG_MAPPED_STORAGE_BASE where appropriate. This CL leaves chip/npcx in a broken state -- it's fixed in a follow-up CL. BRANCH=None BUG=chrome-os-partner:23796 TEST=With entire patch series, on both Samus and Glados: - Verify 'version' EC console command is correct - Verify 'flashrom -p ec -r read.bin' reads back EC image - Verify software sync correctly flashes both EC and PD RW images Change-Id: Idb3c4ed9f7f6edd0a6d49ad11753eba713e67a80 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/297484 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
Diffstat (limited to 'include/config_std_internal_flash.h')
-rw-r--r--include/config_std_internal_flash.h6
1 files changed, 5 insertions, 1 deletions
diff --git a/include/config_std_internal_flash.h b/include/config_std_internal_flash.h
index 10cd5baf5c..51bd011304 100644
--- a/include/config_std_internal_flash.h
+++ b/include/config_std_internal_flash.h
@@ -33,9 +33,13 @@
*/
/* Memory-mapped internal flash w/ PSTATE */
-#define CONFIG_FLASH_MAPPED
+#define CONFIG_INTERNAL_STORAGE
+#define CONFIG_MAPPED_STORAGE
#define CONFIG_FLASH_PSTATE
+/* Program is run directly from storage */
+#define CONFIG_MAPPED_STORAGE_BASE CONFIG_PROGRAM_MEMORY_BASE
+
/*
* The EC uses the one bank of flash to emulate a SPI-like write protect
* register with persistent state.