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| author | Shawn Nematbakhsh <shawnn@chromium.org> | 2015-03-11 18:09:30 -0700 |
|---|---|---|
| committer | ChromeOS Commit Bot <chromeos-commit-bot@chromium.org> | 2015-03-17 01:42:30 +0000 |
| commit | 746debdf20a647fbe0e197f8a6c7b0597bc6a27f (patch) | |
| tree | 11f04a0d74e583f71d0e7cab4c6007db52384fbc /include/config.h | |
| parent | fa671e65917b6673250af23e58372bcec272ca0e (diff) | |
| download | chrome-ec-746debdf20a647fbe0e197f8a6c7b0597bc6a27f.tar.gz | |
spi_flash: Rework protection translation functions
Previously we defined separate functions to map registers to protect
ranges for each supported SPI ROM. This change instead adds a protect range
table + flags for each supported SPI ROM and adds common functions for
translation between ranges + registers. This makes supporting new parts
easier. Since we will never use most supported protection ranges, we can
even simplfy the tables.
The implementation is now similar to flashrom.
BUG=chrome-os-partner:37688
TEST=Manual on Glower.
flashwp disable + spi_flash_rsr --> 0
flashinfo --> shows no protection
spi_flash_prot 0 0x10000 + spi_flash_rsr --> 0x24
flashinfo --> shows 64KB protected
spi_flash_prot 0 0x20000 + spi_flash_rsr --> 0x28
flashinfo --> shows all 96KB protected
spi_flash_prot 0 0x40000 + spi_flash_rsr --> 0x2c
spi_flash_prot 0 0x80000 + spi_flash_rsr --> 0x10
spi_flash_prot 0 0 + spi_flash_rsr --> 0x00
spi_flash_prot 0 0x1000 --> error
spi_flash_prot 0x10000 0x10000 --> error
BRANCH=None
Change-Id: Ie5908ce687b7ff207b09794c7b001a4fbd9e0f5a
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/259310
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Diffstat (limited to 'include/config.h')
| -rw-r--r-- | include/config.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/include/config.h b/include/config.h index eee74b4389..c83258b215 100644 --- a/include/config.h +++ b/include/config.h @@ -1045,6 +1045,9 @@ /* Support W25X40 SPI flash */ #undef CONFIG_SPI_FLASH_W25X40 +/* SPI flash part supports SR2 register */ +#undef CONFIG_SPI_FLASH_HAS_SR2 + /* Size (bytes) of SPI flash memory */ #undef CONFIG_SPI_FLASH_SIZE |