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| author | Mary Ruthven <mruthven@chromium.org> | 2021-01-11 11:27:12 -0800 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2021-01-11 21:55:20 +0000 |
| commit | ec643f0d99397eafa09ab39b2d7dd6b968bd70d8 (patch) | |
| tree | 76109b01c5760134d13384678b5ce126e29fba8c /include/config.h | |
| parent | 17baff2bd51e5b14fa9992f4cddca96742a7dea8 (diff) | |
| download | chrome-ec-ec643f0d99397eafa09ab39b2d7dd6b968bd70d8.tar.gz | |
coil: cleanup commentsstabilize-rust-13720.B-cr50_stab
BUG=b:175244613
TEST=make buildall -j
Change-Id: Icbd143b072fdd5df3b67d7e5a09ee6c01a77f6b9
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2622889
Reviewed-by: Namyoon Woo <namyoon@chromium.org>
Diffstat (limited to 'include/config.h')
| -rw-r--r-- | include/config.h | 18 |
1 files changed, 10 insertions, 8 deletions
diff --git a/include/config.h b/include/config.h index 067ba0b9da..d37fd3ea41 100644 --- a/include/config.h +++ b/include/config.h @@ -2590,13 +2590,13 @@ #undef CONFIG_HOSTCMD_ESPI_VW_SLP_S3 #undef CONFIG_HOSTCMD_ESPI_VW_SLP_S4 -/* MCHP next two items are EC eSPI slave configuration */ -/* Maximum clock frequence eSPI EC slave advertises +/* MCHP next two items are EC eSPI peripheral configuration */ +/* Maximum clock frequence eSPI EC peripheral advertises * Values in MHz are 20, 25, 33, 50, and 66 */ #undef CONFIG_HOSTCMD_ESPI_EC_MAX_FREQ -/* EC eSPI slave advertises IO lanes +/* EC eSPI peripheral advertises IO lanes * 0 = Single * 1 = Single and Dual * 2 = Single and Quad @@ -3138,17 +3138,19 @@ */ #undef CONFIG_SPI_NOR_SMART_ERASE -/* SPI master feature */ +/* SPI controller feature */ #undef CONFIG_SPI_CONTROLLER -/* SPI master halfduplex/3-wire mode */ +/* SPI controller halfduplex/3-wire mode */ #undef CONFIG_SPI_HALFDUPLEX -/* SPI master configure gpios on init */ +/* SPI controller configure gpios on init */ #undef CONFIG_SPI_CONTROLLER_CONFIGURE_GPIOS -/* Support SPI masters without GPIO-specified Chip Selects, instead rely on the - * SPI master port's hardwired CS pin. */ +/* + * Support SPI controller's without GPIO-specified Chip Selects, instead rely on + * the SPI controller port's hardwired CS pin. + */ #undef CONFIG_SPI_CONTROLLER_NO_CS_GPIOS /* Support testing SPI periph interface driver. */ |