usb_spi: move to Raiden V2 implementation

This patch introduces an alternative USB SPI protocol implementation
to be used by Cr50: Raiden V2. The SPI USB endpoint descriptor is
modified to advertise the new version in the bInterfaceProtocol, which
allows the flashrom utility to use the new protocol version.

Protocol version 2 implements segmentation and reassembly where longer
flash read and write PDUs can be transferred split into shorter fixed
size USB packets. The comment section in usb_spi_v2.c describes the
protocol in detail.

Each time a USB packet is received from the host, the packet header is
examined to determine the command. The command could be a DUT
configuration query OR a request to read and or write some data
from/to the SPI flash chip, OR a request to retransmit the last PDU
from the beginning.

This patch implementation does not process the retransmittion request
command yet, in case a packet is dropped flashrom would need to be
re-run. This is a pretty rare condition, but if deemed necessary
support can be added later.

H1 SPI controller supports multibuffer transactions where the CS
signal is kept asserted while the controller clocks the bus when the
next portion of data to write becomes available or there is more room
to read data to send back to the host. This allows to support
arbitrary length read and write transactions. There is no need to
support write transactions longer than 256 bytes of data, as this is a
typical SPI flash chip page size. For read direction the size of 2040
was chosen, which is close to 2K and takes full payload of 34 USB
packets on top of 2 byte headers.

The protocol state machine on the device sideOB can be in one of
two states, IDLE or WRITING. Many of host requests do not require the
device to change state: configuration requests, or writes of short
blocks of data (fitting into one USB packet) can be executed
immediately. Requests to read long blocks of data can still be
executed without leaving the IDLE state, the device starts the SPI
transaction and then iterates reading one packet worth of data at a
time and sends it back to the host. Once the entire PDU is read, the
CS is deasserted.

In case the host requests to write a block of data which does not fit
into a USB packet the device asserts the CS, sends the first received
block to the SPI flash chip and then enters the WRITING state,
expecting the controller to send the rest of the PDU in following
packets.

Once the entire PDU is transferred the CS is deasserted and state is
changed back to IDLE.

BUG=b:79492818
TEST=performed numerous flash read/write operations with 16M SPI flash
     chip on the Atlas device. Timing results comparison of various
     operations:
                                  Raiden V1         Raiden V2

  Reading entire chip:              3m 16s            0m 52s

  Vanilla writing of new image:    16m 22s            5m 48s

  Writing of AP firmware into an
  erased flash chip (no read
  before or after writing)          4m 12s            1m 38s

Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Change-Id: I374f3caab7146fc84b62274e9e713430d7d31de0
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2977965
Reviewed-by: Brian Nemec <bnemec@chromium.org>
Reviewed-by: Andrey Pronin <apronin@chromium.org>

1 files changed, 3 insertions, 1 deletions

diff --git a/include/config.h b/include/config.h
index 5bab6a1c08..7f334bd5dc 100644
--- a/include/config.h
+++ b/include/config.h
@@ -4066,8 +4066,10 @@
 #undef CONFIG_USB_GPIO
 
 /*****************************************************************************/
-/* USB SPI config */
+/* USB SPI legacy protocol (V1). */
 #undef CONFIG_USB_SPI
+/* USB_SPI protocol V2. */
+#undef CONFIG_USB_SPI_V2
 
 /*****************************************************************************/
 /* USB I2C config */