diff options
author | Vic Yang <victoryang@google.com> | 2015-02-04 11:28:53 -0800 |
---|---|---|
committer | ChromeOS Commit Bot <chromeos-commit-bot@chromium.org> | 2015-02-10 10:47:07 +0000 |
commit | 049463f8ad985f9cb996caa7dbc5438383bd3084 (patch) | |
tree | 93ff78695657a998919c6d6e28101cd158489368 /include/clock.h | |
parent | a9ae00b10129feca28713a7b88978ff6cfe7c2a6 (diff) | |
download | chrome-ec-049463f8ad985f9cb996caa7dbc5438383bd3084.tar.gz |
stm32: Add delay after enabling peripheral clock
We need a dummy read after enabling AHB peripheral clock before we can
access the peripheral. For APB, we also need a dummy read for STM32F3.
BRANCH=All affected
BUG=chrome-os-partner:33007
TEST=make buildall
Change-Id: I47f4a024dca294f555428c3f2053c1d32835ebe0
Signed-off-by: Vic Yang <victoryang@google.com>
Reviewed-on: https://chromium-review.googlesource.com/246181
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Tested-by: Vic Yang <victoryang@chromium.org>
Commit-Queue: Vic Yang <victoryang@chromium.org>
Diffstat (limited to 'include/clock.h')
-rw-r--r-- | include/clock.h | 17 |
1 files changed, 16 insertions, 1 deletions
diff --git a/include/clock.h b/include/clock.h index 62c38bcd6a..7702ca85eb 100644 --- a/include/clock.h +++ b/include/clock.h @@ -47,7 +47,7 @@ void clock_enable_module(enum module_id module, int enable); void clock_enable_pll(int enable, int notify); /** - * Wait for a number of clock cycles. + * Wait for a number of CPU clock cycles. * * Simple busy waiting for use before clocks/timers are initialized. * @@ -55,6 +55,21 @@ void clock_enable_pll(int enable, int notify); */ void clock_wait_cycles(uint32_t cycles); +enum bus_type { + BUS_AHB, + BUS_APB, +}; + +/** + * Wait for a number of peripheral bus clock cycles. + * + * Dummy read on peripherals for delay. + * + * @param bus Which bus clock cycle to use. + * @param cycles Number of cycles to wait. + */ +void clock_wait_bus_cycles(enum bus_type bus, uint32_t cycles); + /* Clock gate control modes for clock_enable_peripheral() */ #define CGC_MODE_RUN (1 << 0) #define CGC_MODE_SLEEP (1 << 1) |