STM32L ADC driver

ADC module on STM32L is clocked by HSI oscillator, and thus we need to
switch to HSI if using MSI. After the conversion, if the system is not
in S0, clock is switched back to MSI again.

There are several register bits that can only be written when ADC is
powered down. For now, let's just power down the ADC after each
conversion.

Currently ADC watchdog is not working and is disabled on STM32L.

BUG=chrome-os-partner:22242
TEST=Try multiple all-channel and single-channel reads in S0 and S5.
BRANCH=None

Change-Id: I769dda8a9c69ac9de1eb22d6d259034eef8c1ac4
Signed-off-by: Vic Yang <victoryang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/167454

1 files changed, 16 insertions, 0 deletions

diff --git a/include/clock.h b/include/clock.h
index e70df962b1..6703249076 100644
--- a/include/clock.h
+++ b/include/clock.h
@@ -21,6 +21,22 @@ void clock_init(void);
 int clock_get_freq(void);
 
 /**
+ * Enable or disable clock for a module.
+ *
+ * Note that if the module requires a higher system clock speed than the
+ * current system clock speed, the entire system clock will be increased
+ * to allow the module to operate.
+ *
+ * When a module is disabled, the system clock will be reduced to the highest
+ * clock required by the remaining enabled modules.
+ *
+ * @param module        The module for which we need to enable/disable its
+ *                      clock.
+ * @param enable	Enable clock if non-zero; disable if zero.
+ */
+void clock_enable_module(enum module_id module, int enable);
+
+/**
  * Enable or disable the PLL.
  *
  * @param enable	Enable PLL if non-zero; disable if zero.