ppc: nx20p3483: Rename driver to nx20p348x to support NX20P3481

This CL doesn't change any functionality, but renames the driver from
3483 to 348x. The motivation for this is that we need to support the
NX20P3481 PPC as well. Those chips use the same registers, but the
3481 adds FRS support and sink/source control is done via I2C writes
instead of gpio controls.

Because the chips are slighlty different the config option
CONFIG_USBC_PPC_NX20P3483 needs to remain.

BUG=b:111281797
BRANCH=none
TEST=make -j buildall

Change-Id: Ie1085140eb2ef23c0b6e1a79a6f2d7f823326c6d
Signed-off-by: Scott Collyer <scollyer@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1176382
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>

4 files changed, 194 insertions, 194 deletions

diff --git a/driver/build.mk b/driver/build.mk
index 44673c07bf..ad3283ce3c 100644
--- a/driver/build.mk
+++ b/driver/build.mk
@@ -126,7 +126,7 @@ driver-$(CONFIG_USB_MUX_VIRTUAL)+=usb_mux_virtual.o
 
 # Type-C Power Path Controllers (PPC)
 driver-$(CONFIG_USBC_PPC_SN5S330)+=ppc/sn5s330.o
-driver-$(CONFIG_USBC_PPC_NX20P3483)+=ppc/nx20p3483.o
+driver-$(CONFIG_USBC_PPC_NX20P3483)+=ppc/nx20p348x.o
 
 # video converters
 driver-$(CONFIG_MCDP28X0)+=mcdp28x0.o
diff --git a/driver/ppc/nx20p3483.h b/driver/ppc/nx20p3483.h
deleted file mode 100644
index f0979646e1..0000000000
--- a/driver/ppc/nx20p3483.h
+++ /dev/null
@@ -1,113 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* NX20P3483 Type-C Power Path Controller */
-
-#ifndef __CROS_EC_NX20P3483_H
-#define __CROS_EC_NX20P3483_H
-
-#define NX20P3483_ADDR0 0xE0
-#define NX20P3483_ADDR1 0xE2
-#define NX20P3483_ADDR2 0xE4
-#define NX20P3483_ADDR3 0xE6
-
-/*
- * This PPC hard-codes the over voltage protect of Vbus at 6.8V in dead-battery
- * mode. If we ever are every going to drop the PD rail, we need to first ensure
- * that Vbus is negotiated to below 6.8V otherwise we can lock out Vbus.
- */
-#define NX20P3483_SAFE_RESET_VBUS_MV 5000
-
-/* NX20P3483 register addresses */
-#define NX20P3483_DEVICE_ID_REG		0x00
-#define NX20P3483_DEVICE_STATUS_REG		0x01
-#define NX20P3483_SWITCH_CONTROL_REG		0x02
-#define NX20P3483_SWITCH_STATUS_REG		0x03
-#define NX20P3483_INTERRUPT1_REG		0x04
-#define NX20P3483_INTERRUPT2_REG		0x05
-#define NX20P3483_INTERRUPT1_MASK_REG		0x06
-#define NX20P3483_INTERRUPT2_MASK_REG		0x07
-#define NX20P3483_OVLO_THRESHOLD_REG		0x08
-#define NX20P3483_HV_SRC_OCP_THRESHOLD_REG	0x09
-#define NX20P3483_5V_SRC_OCP_THRESHOLD_REG	0x0A
-#define NX20P3483_DEVICE_CONTROL_REG		0x0B
-
-/* Device Control Register */
-#define NX20P3483_CTRL_FRS_AT (1 << 3)
-#define NX20P3483_CTRL_DB_EXIT (1 << 2)
-#define NX20P3483_CTRL_VBUSDIS_EN (1 << 1)
-#define NX20P3483_CTRL_LDO_SD (1 << 0)
-
-/* Device Status Modes */
-#define NX20P3483_DEVICE_MODE_MASK 0x7
-#define NX20P3483_MODE_DEAD_BATTERY 0
-#define NX20P3483_MODE_HV_SNK  1
-#define NX20P3483_MODE_5V_SRC  2
-#define NX20P3483_MODE_HV_SRC  3
-#define NX20P3483_MODE_STANDBY 4
-
-/* Switch Status Register */
-#define NX20P3483_HVSNK_STS (1 << 0)
-#define NX20P3483_HVSRC_STS (1 << 1)
-#define NX20P3483_5VSRC_STS (1 << 2)
-
-/* Internal 5V VBUS Switch Current Limit Settings (min) */
-#define NX20P3483_ILIM_MASK 0xF
-#define NX20P3483_ILIM_0_400  0
-#define NX20P3483_ILIM_0_600  1
-#define NX20P3483_ILIM_0_800  2
-#define NX20P3483_ILIM_1_000  3
-#define NX20P3483_ILIM_1_200  4
-#define NX20P3483_ILIM_1_400  5
-#define NX20P3483_ILIM_1_600  6
-#define NX20P3483_ILIM_1_800  7
-#define NX20P3483_ILIM_2_000  8
-#define NX20P3483_ILIM_2_200  9
-#define NX20P3483_ILIM_2_400 10
-#define NX20P3483_ILIM_2_600 11
-#define NX20P3483_ILIM_2_800 12
-#define NX20P3483_ILIM_3_000 13
-#define NX20P3483_ILIM_3_200 14
-#define NX20P3483_ILIM_3_400 15
-
-/* HV VBUS over voltage threshold settings V_mV*/
-#define NX20P3483_OVLO_THRESHOLD_MASK 0x7
-#define NX20P3483_OVLO_06_0 0
-#define NX20P3483_OVLO_06_8 1
-#define NX20P3483_OVLO_10_0 2
-#define NX20P3483_OVLO_11_5 3
-#define NX20P3483_OVLO_14_0 4
-#define NX20P3483_OVLO_17_0 5
-#define NX20P3483_OVLO_23_0 6
-
-/* Interrupt 1 Register Bits */
-#define NX20P3483_INT1_DBEXIT_ERR (1 << 7)
-#define NX20P3483_INT1_OV_5VSRC   (1 << 4)
-#define NX20P3483_INT1_RCP_5VSRC  (1 << 3)
-#define NX20P3483_INT1_SC_5VSRC   (1 << 2)
-#define NX20P3483_INT1_OC_5VSRC   (1 << 1)
-#define NX20P3483_INT1_OTP        (1 << 0)
-
-/* Interrupt 2 Register Bits */
-#define NX20P3483_INT2_EN_ERR     (1 << 7)
-#define NX20P3483_INT2_RCP_HVSNK  (1 << 6)
-#define NX20P3483_INT2_SC_HVSNK   (1 << 5)
-#define NX20P3483_INT2_OV_HVSNK   (1 << 4)
-#define NX20P3483_INT2_RCP_HVSRC  (1 << 3)
-#define NX20P3483_INT2_SC_HVSRC   (1 << 2)
-#define NX20P3483_INT2_OC_HVSRC   (1 << 1)
-#define NX20P3483_INT2_OV_HVSRC   (1 << 0)
-
-struct ppc_drv;
-extern const struct ppc_drv nx20p3483_drv;
-
-/**
- * Interrupt Handler for the NX20P3483.
- *
- * @param port: The Type-C port which triggered the interrupt.
- */
-void nx20p3483_interrupt(int port);
-
-#endif /* defined(__CROS_EC_NX20P3483_H) */
diff --git a/driver/ppc/nx20p3483.c b/driver/ppc/nx20p348x.c
index 9609be7dcd..a5ee9d5e31 100644
--- a/driver/ppc/nx20p3483.c
+++ b/driver/ppc/nx20p348x.c
@@ -3,11 +3,11 @@
  * found in the LICENSE file.
  */
 
-/* NX20P3483 USB-C Power Path Controller */
+/* NX20P348x USB-C Power Path Controller */
 
 #include "common.h"
 #include "console.h"
-#include "driver/ppc/nx20p3483.h"
+#include "driver/ppc/nx20p348x.h"
 #include "gpio.h"
 #include "hooks.h"
 #include "i2c.h"
@@ -23,10 +23,10 @@
 
 static uint32_t irq_pending; /* Bitmask of ports signaling an interrupt. */
 
-#define NX20P3483_DB_EXIT_FAIL_THRESHOLD 10
+#define NX20P348X_DB_EXIT_FAIL_THRESHOLD 10
 static int db_exit_fail_count[CONFIG_USB_PD_PORT_COUNT];
 
-#define NX20P3483_FLAGS_SOURCE_ENABLED (1 << 0)
+#define NX20P348X_FLAGS_SOURCE_ENABLED (1 << 0)
 static uint8_t flags[CONFIG_USB_PD_PORT_COUNT];
 
 static int read_reg(uint8_t port, int reg, int *regval)
@@ -45,78 +45,78 @@ static int write_reg(uint8_t port, int reg, int regval)
 			  regval);
 }
 
-static int nx20p3483_set_ovp_limit(int port)
+static int nx20p348x_set_ovp_limit(int port)
 {
 	int rv;
 	int reg;
 
 	/* Set VBUS over voltage threshold (OVLO) */
-	rv = read_reg(port, NX20P3483_OVLO_THRESHOLD_REG, &reg);
+	rv = read_reg(port, NX20P348X_OVLO_THRESHOLD_REG, &reg);
 	if (rv)
 		return rv;
 	/* OVLO threshold is 3 bit field */
-	reg &= ~NX20P3483_OVLO_THRESHOLD_MASK;
+	reg &= ~NX20P348X_OVLO_THRESHOLD_MASK;
 	/* Set SNK OVP to 23.0 V */
-	reg |= NX20P3483_OVLO_23_0;
-	rv = write_reg(port, NX20P3483_OVLO_THRESHOLD_REG, reg);
+	reg |= NX20P348X_OVLO_23_0;
+	rv = write_reg(port, NX20P348X_OVLO_THRESHOLD_REG, reg);
 	if (rv)
 		return rv;
 
 	return EC_SUCCESS;
 }
 
-static int nx20p3483_is_sourcing_vbus(int port)
+static int nx20p348x_is_sourcing_vbus(int port)
 {
-	return flags[port] & NX20P3483_FLAGS_SOURCE_ENABLED;
+	return flags[port] & NX20P348X_FLAGS_SOURCE_ENABLED;
 }
 
-static int nx20p3483_set_vbus_source_current_limit(int port,
+static int nx20p348x_set_vbus_source_current_limit(int port,
 						 enum tcpc_rp_value rp)
 {
 	int regval;
 	int status;
 
-	status = read_reg(port, NX20P3483_5V_SRC_OCP_THRESHOLD_REG, &regval);
+	status = read_reg(port, NX20P348X_5V_SRC_OCP_THRESHOLD_REG, &regval);
 	if (status)
 		return status;
 
-	regval &= ~NX20P3483_ILIM_MASK;
+	regval &= ~NX20P348X_ILIM_MASK;
 
 	/* We need buffer room for all current values. */
 	switch (rp) {
 	case TYPEC_RP_3A0:
-		regval |= NX20P3483_ILIM_3_200;
+		regval |= NX20P348X_ILIM_3_200;
 		break;
 
 	case TYPEC_RP_1A5:
-		regval |= NX20P3483_ILIM_1_600;
+		regval |= NX20P348X_ILIM_1_600;
 		break;
 
 	case TYPEC_RP_USB:
 	default:
-		regval |= NX20P3483_ILIM_0_600;
+		regval |= NX20P348X_ILIM_0_600;
 		break;
 	};
 
 
-	return write_reg(port, NX20P3483_5V_SRC_OCP_THRESHOLD_REG, regval);
+	return write_reg(port, NX20P348X_5V_SRC_OCP_THRESHOLD_REG, regval);
 }
 
-static int nx20p3483_discharge_vbus(int port, int enable)
+static int nx20p348x_discharge_vbus(int port, int enable)
 {
 	int regval;
 	int status;
 
-	status = read_reg(port, NX20P3483_DEVICE_CONTROL_REG, &regval);
+	status = read_reg(port, NX20P348X_DEVICE_CONTROL_REG, &regval);
 	if (status)
 		return status;
 
 	if (enable)
-		regval |= NX20P3483_CTRL_VBUSDIS_EN;
+		regval |= NX20P348X_CTRL_VBUSDIS_EN;
 	else
-		regval &= ~NX20P3483_CTRL_VBUSDIS_EN;
+		regval &= ~NX20P348X_CTRL_VBUSDIS_EN;
 
-	status = write_reg(port, NX20P3483_DEVICE_CONTROL_REG, regval);
+	status = write_reg(port, NX20P348X_DEVICE_CONTROL_REG, regval);
 	if (status) {
 		CPRINTS("Failed to %s vbus discharge",
 			enable ? "enable" : "disable");
@@ -126,12 +126,12 @@ static int nx20p3483_discharge_vbus(int port, int enable)
 	return EC_SUCCESS;
 }
 
-static int nx20p3483_vbus_sink_enable(int port, int enable)
+static int nx20p348x_vbus_sink_enable(int port, int enable)
 {
 	int status;
 	int rv;
-	int desired_mode = enable ? NX20P3483_MODE_HV_SNK :
-		NX20P3483_MODE_STANDBY;
+	int desired_mode = enable ? NX20P348X_MODE_HV_SNK :
+		NX20P348X_MODE_STANDBY;
 
 	enable = !!enable;
 
@@ -144,20 +144,20 @@ static int nx20p3483_vbus_sink_enable(int port, int enable)
 		return rv;
 
 	/* Read device status register to get mode */
-	rv = read_reg(port, NX20P3483_DEVICE_STATUS_REG, &status);
+	rv = read_reg(port, NX20P348X_DEVICE_STATUS_REG, &status);
 	if (rv)
 		return rv;
 
-	return ((status & NX20P3483_DEVICE_MODE_MASK) == desired_mode) ?
+	return ((status & NX20P348X_DEVICE_MODE_MASK) == desired_mode) ?
 		EC_SUCCESS : EC_ERROR_UNKNOWN;
 }
 
-static int nx20p3483_vbus_source_enable(int port, int enable)
+static int nx20p348x_vbus_source_enable(int port, int enable)
 {
 	int status;
 	int rv;
-	int desired_mode = enable ? NX20P3483_MODE_5V_SRC :
-		NX20P3483_MODE_STANDBY;
+	int desired_mode = enable ? NX20P348X_MODE_5V_SRC :
+		NX20P348X_MODE_STANDBY;
 
 	enable = !!enable;
 
@@ -170,23 +170,23 @@ static int nx20p3483_vbus_source_enable(int port, int enable)
 		return rv;
 
 	/* Read device status register to get mode */
-	rv = read_reg(port, NX20P3483_DEVICE_STATUS_REG, &status);
+	rv = read_reg(port, NX20P348X_DEVICE_STATUS_REG, &status);
 	if (rv)
 		return rv;
 
-	if ((status & NX20P3483_DEVICE_MODE_MASK) != desired_mode)
+	if ((status & NX20P348X_DEVICE_MODE_MASK) != desired_mode)
 		return EC_ERROR_UNKNOWN;
 
 	/* Cache the Vbus state */
 	if (enable)
-		flags[port] |= NX20P3483_FLAGS_SOURCE_ENABLED;
+		flags[port] |= NX20P348X_FLAGS_SOURCE_ENABLED;
 	else
-		flags[port] &= ~NX20P3483_FLAGS_SOURCE_ENABLED;
+		flags[port] &= ~NX20P348X_FLAGS_SOURCE_ENABLED;
 
 	return EC_SUCCESS;
 }
 
-static int nx20p3483_init(int port)
+static int nx20p348x_init(int port)
 {
 	int reg;
 	int mask;
@@ -194,29 +194,29 @@ static int nx20p3483_init(int port)
 	int rv;
 
 	/* Mask interrupts for interrupt 2 register */
-	mask = ~NX20P3483_INT2_EN_ERR;
-	rv = write_reg(port, NX20P3483_INTERRUPT2_MASK_REG, mask);
+	mask = ~NX20P348X_INT2_EN_ERR;
+	rv = write_reg(port, NX20P348X_INTERRUPT2_MASK_REG, mask);
 	if (rv)
 		return rv;
 
 	/* Mask interrupts for interrupt 1 register */
-	mask = ~(NX20P3483_INT1_OC_5VSRC | NX20P3483_INT1_DBEXIT_ERR);
-	rv = write_reg(port, NX20P3483_INTERRUPT1_MASK_REG, mask);
+	mask = ~(NX20P348X_INT1_OC_5VSRC | NX20P348X_INT1_DBEXIT_ERR);
+	rv = write_reg(port, NX20P348X_INTERRUPT1_MASK_REG, mask);
 	if (rv)
 		return rv;
 
 	/* Clear any pending interrupts by reading interrupt registers */
-	read_reg(port, NX20P3483_INTERRUPT1_REG, &reg);
-	read_reg(port, NX20P3483_INTERRUPT2_REG, &reg);
+	read_reg(port, NX20P348X_INTERRUPT1_REG, &reg);
+	read_reg(port, NX20P348X_INTERRUPT2_REG, &reg);
 
 	/* Get device  mode */
-	rv = read_reg(port, NX20P3483_DEVICE_STATUS_REG, &mode);
+	rv = read_reg(port, NX20P348X_DEVICE_STATUS_REG, &mode);
 	if (rv)
 		return rv;
-	mode &= NX20P3483_DEVICE_MODE_MASK;
+	mode &= NX20P348X_DEVICE_MODE_MASK;
 
 	/* Check if dead battery mode is active. */
-	if (mode == NX20P3483_MODE_DEAD_BATTERY) {
+	if (mode == NX20P348X_MODE_DEAD_BATTERY) {
 		/*
 		 * If in dead battery mode, must enable HV SNK mode prior to
 		 * exiting dead battery mode or VBUS path will get cut off and
@@ -224,14 +224,14 @@ static int nx20p3483_init(int port)
 		 * mode will not reflect the correct value and therefore the
 		 * return value isn't useful here.
 		 */
-		nx20p3483_vbus_sink_enable(port, 1);
+		nx20p348x_vbus_sink_enable(port, 1);
 
 		/* Exit dead battery mode. */
-		rv = read_reg(port, NX20P3483_DEVICE_CONTROL_REG, &reg);
+		rv = read_reg(port, NX20P348X_DEVICE_CONTROL_REG, &reg);
 		if (rv)
 			return rv;
-		reg |= NX20P3483_CTRL_DB_EXIT;
-		rv = write_reg(port, NX20P3483_DEVICE_CONTROL_REG, reg);
+		reg |= NX20P348X_CTRL_DB_EXIT;
+		rv = write_reg(port, NX20P348X_DEVICE_CONTROL_REG, reg);
 		if (rv)
 			return rv;
 	}
@@ -241,12 +241,12 @@ static int nx20p3483_init(int port)
 	 * dead battery mode, OVLO is forced to 6.8V, so this setting must be
 	 * done after dead battery mode is exited.
 	 */
-	nx20p3483_set_ovp_limit(port);
+	nx20p348x_set_ovp_limit(port);
 
 	return EC_SUCCESS;
 }
 
-static void nx20p3483_handle_interrupt(int port)
+static void nx20p348x_handle_interrupt(int port)
 {
 	int reg;
 	int control_reg;
@@ -255,10 +255,10 @@ static void nx20p3483_handle_interrupt(int port)
 	 * Read interrupt 1 status register. Note, interrupt register is
 	 * automatically cleared by reading.
 	 */
-	read_reg(port, NX20P3483_INTERRUPT1_REG, &reg);
+	read_reg(port, NX20P348X_INTERRUPT1_REG, &reg);
 
 	/* Check for DBEXIT error */
-	if (reg & NX20P3483_INT1_DBEXIT_ERR) {
+	if (reg & NX20P348X_INT1_DBEXIT_ERR) {
 		int mask_reg;
 
 		/*
@@ -267,28 +267,28 @@ static void nx20p3483_handle_interrupt(int port)
 		 * prevent interrupt floods.
 		 */
 		if (++db_exit_fail_count[port] >=
-		    NX20P3483_DB_EXIT_FAIL_THRESHOLD) {
+		    NX20P348X_DB_EXIT_FAIL_THRESHOLD) {
 			CPRINTS("Port %d PPC failed to exit DB mode", port);
-			if (read_reg(port, NX20P3483_INTERRUPT1_MASK_REG,
+			if (read_reg(port, NX20P348X_INTERRUPT1_MASK_REG,
 				    &mask_reg)) {
-				mask_reg |= NX20P3483_INT1_DBEXIT_ERR;
-				write_reg(port, NX20P3483_INTERRUPT1_MASK_REG,
+				mask_reg |= NX20P348X_INT1_DBEXIT_ERR;
+				write_reg(port, NX20P348X_INTERRUPT1_MASK_REG,
 					  mask_reg);
 			}
 		}
-		read_reg(port, NX20P3483_DEVICE_CONTROL_REG, &control_reg);
-		reg |= NX20P3483_CTRL_DB_EXIT;
-		write_reg(port, NX20P3483_DEVICE_CONTROL_REG, control_reg);
+		read_reg(port, NX20P348X_DEVICE_CONTROL_REG, &control_reg);
+		reg |= NX20P348X_CTRL_DB_EXIT;
+		write_reg(port, NX20P348X_DEVICE_CONTROL_REG, control_reg);
 		/*
 		 * If DB exit mode failed, then the OVP limit setting done in
 		 * the init routine will not be successful. Set the OVP limit
 		 * again here.
 		 */
-		nx20p3483_set_ovp_limit(port);
+		nx20p348x_set_ovp_limit(port);
 	}
 
 	/* Check for 5V OC interrupt */
-	if (reg & NX20P3483_INT1_OC_5VSRC) {
+	if (reg & NX20P348X_INT1_OC_5VSRC) {
 		CPRINTS("C%d: PPC detected overcurrent!", port);
 		/*
 		 * TODO (b/69935262): The overcurrent action hasn't
@@ -308,36 +308,36 @@ static void nx20p3483_handle_interrupt(int port)
 	 * these values aren't controlled by the EC directly, not sure what
 	 * action if any can be taken.
 	 */
-	read_reg(port, NX20P3483_INTERRUPT2_REG, &reg);
+	read_reg(port, NX20P348X_INTERRUPT2_REG, &reg);
 }
 
-static void nx20p3483_irq_deferred(void)
+static void nx20p348x_irq_deferred(void)
 {
 	int i;
 	uint32_t pending = atomic_read_clear(&irq_pending);
 
 	for (i = 0; i < CONFIG_USB_PD_PORT_COUNT; i++)
 		if ((1 << i) & pending)
-			nx20p3483_handle_interrupt(i);
+			nx20p348x_handle_interrupt(i);
 }
-DECLARE_DEFERRED(nx20p3483_irq_deferred);
+DECLARE_DEFERRED(nx20p348x_irq_deferred);
 
-void nx20p3483_interrupt(int port)
+void nx20p348x_interrupt(int port)
 {
 	atomic_or(&irq_pending, (1 << port));
-	hook_call_deferred(&nx20p3483_irq_deferred_data, 0);
+	hook_call_deferred(&nx20p348x_irq_deferred_data, 0);
 }
 
 #ifdef CONFIG_CMD_PPC_DUMP
-static int nx20p3483_dump(int port)
+static int nx20p348x_dump(int port)
 {
 	int reg_addr;
 	int reg;
 	int rv;
 
-	ccprintf("Port %d NX20P3483 registers\n", port);
-	for (reg_addr = NX20P3483_DEVICE_ID_REG; reg_addr <=
-		     NX20P3483_DEVICE_CONTROL_REG; reg_addr++) {
+	ccprintf("Port %d NX20P348X registers\n", port);
+	for (reg_addr = NX20P348X_DEVICE_ID_REG; reg_addr <=
+		     NX20P348X_DEVICE_CONTROL_REG; reg_addr++) {
 		rv = read_reg(port, reg_addr, &reg);
 		if (rv) {
 			ccprintf("nx20p: Failed to read register 0x%x\n",
@@ -354,15 +354,15 @@ static int nx20p3483_dump(int port)
 }
 #endif /* defined(CONFIG_CMD_PPC_DUMP) */
 
-const struct ppc_drv nx20p3483_drv = {
-	.init = &nx20p3483_init,
-	.is_sourcing_vbus = &nx20p3483_is_sourcing_vbus,
-	.vbus_sink_enable = &nx20p3483_vbus_sink_enable,
-	.vbus_source_enable = &nx20p3483_vbus_source_enable,
+const struct ppc_drv nx20p348x_drv = {
+	.init = &nx20p348x_init,
+	.is_sourcing_vbus = &nx20p348x_is_sourcing_vbus,
+	.vbus_sink_enable = &nx20p348x_vbus_sink_enable,
+	.vbus_source_enable = &nx20p348x_vbus_source_enable,
 #ifdef CONFIG_CMD_PPC_DUMP
-	.reg_dump = &nx20p3483_dump,
+	.reg_dump = &nx20p348x_dump,
 #endif /* defined(CONFIG_CMD_PPC_DUMP) */
 	.set_vbus_source_current_limit =
-		&nx20p3483_set_vbus_source_current_limit,
-	.discharge_vbus = &nx20p3483_discharge_vbus,
+		&nx20p348x_set_vbus_source_current_limit,
+	.discharge_vbus = &nx20p348x_discharge_vbus,
 };
diff --git a/driver/ppc/nx20p348x.h b/driver/ppc/nx20p348x.h
new file mode 100644
index 0000000000..52224b6a8e
--- /dev/null
+++ b/driver/ppc/nx20p348x.h
@@ -0,0 +1,113 @@
+/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* NX20P348x Type-C Power Path Controller */
+
+#ifndef __CROS_EC_NX20P348X_H
+#define __CROS_EC_NX20P348X_H
+
+#define NX20P3483_ADDR0 0xE0
+#define NX20P3483_ADDR1 0xE2
+#define NX20P3483_ADDR2 0xE4
+#define NX20P3483_ADDR3 0xE6
+
+/*
+ * This PPC hard-codes the over voltage protect of Vbus at 6.8V in dead-battery
+ * mode. If we ever are every going to drop the PD rail, we need to first ensure
+ * that Vbus is negotiated to below 6.8V otherwise we can lock out Vbus.
+ */
+#define NX20P348X_SAFE_RESET_VBUS_MV 5000
+
+/* NX20P348x register addresses */
+#define NX20P348X_DEVICE_ID_REG		0x00
+#define NX20P348X_DEVICE_STATUS_REG		0x01
+#define NX20P348X_SWITCH_CONTROL_REG		0x02
+#define NX20P348X_SWITCH_STATUS_REG		0x03
+#define NX20P348X_INTERRUPT1_REG		0x04
+#define NX20P348X_INTERRUPT2_REG		0x05
+#define NX20P348X_INTERRUPT1_MASK_REG		0x06
+#define NX20P348X_INTERRUPT2_MASK_REG		0x07
+#define NX20P348X_OVLO_THRESHOLD_REG		0x08
+#define NX20P348X_HV_SRC_OCP_THRESHOLD_REG	0x09
+#define NX20P348X_5V_SRC_OCP_THRESHOLD_REG	0x0A
+#define NX20P348X_DEVICE_CONTROL_REG		0x0B
+
+/* Device Control Register */
+#define NX20P348X_CTRL_FRS_AT (1 << 3)
+#define NX20P348X_CTRL_DB_EXIT (1 << 2)
+#define NX20P348X_CTRL_VBUSDIS_EN (1 << 1)
+#define NX20P348X_CTRL_LDO_SD (1 << 0)
+
+/* Device Status Modes */
+#define NX20P348X_DEVICE_MODE_MASK 0x7
+#define NX20P348X_MODE_DEAD_BATTERY 0
+#define NX20P348X_MODE_HV_SNK  1
+#define NX20P348X_MODE_5V_SRC  2
+#define NX20P348X_MODE_HV_SRC  3
+#define NX20P348X_MODE_STANDBY 4
+
+/* Switch Status Register */
+#define NX20P348X_HVSNK_STS (1 << 0)
+#define NX20P348X_HVSRC_STS (1 << 1)
+#define NX20P348X_5VSRC_STS (1 << 2)
+
+/* Internal 5V VBUS Switch Current Limit Settings (min) */
+#define NX20P348X_ILIM_MASK 0xF
+#define NX20P348X_ILIM_0_400  0
+#define NX20P348X_ILIM_0_600  1
+#define NX20P348X_ILIM_0_800  2
+#define NX20P348X_ILIM_1_000  3
+#define NX20P348X_ILIM_1_200  4
+#define NX20P348X_ILIM_1_400  5
+#define NX20P348X_ILIM_1_600  6
+#define NX20P348X_ILIM_1_800  7
+#define NX20P348X_ILIM_2_000  8
+#define NX20P348X_ILIM_2_200  9
+#define NX20P348X_ILIM_2_400 10
+#define NX20P348X_ILIM_2_600 11
+#define NX20P348X_ILIM_2_800 12
+#define NX20P348X_ILIM_3_000 13
+#define NX20P348X_ILIM_3_200 14
+#define NX20P348X_ILIM_3_400 15
+
+/* HV VBUS over voltage threshold settings V_mV*/
+#define NX20P348X_OVLO_THRESHOLD_MASK 0x7
+#define NX20P348X_OVLO_06_0 0
+#define NX20P348X_OVLO_06_8 1
+#define NX20P348X_OVLO_10_0 2
+#define NX20P348X_OVLO_11_5 3
+#define NX20P348X_OVLO_14_0 4
+#define NX20P348X_OVLO_17_0 5
+#define NX20P348X_OVLO_23_0 6
+
+/* Interrupt 1 Register Bits */
+#define NX20P348X_INT1_DBEXIT_ERR (1 << 7)
+#define NX20P348X_INT1_OV_5VSRC   (1 << 4)
+#define NX20P348X_INT1_RCP_5VSRC  (1 << 3)
+#define NX20P348X_INT1_SC_5VSRC   (1 << 2)
+#define NX20P348X_INT1_OC_5VSRC   (1 << 1)
+#define NX20P348X_INT1_OTP        (1 << 0)
+
+/* Interrupt 2 Register Bits */
+#define NX20P348X_INT2_EN_ERR     (1 << 7)
+#define NX20P348X_INT2_RCP_HVSNK  (1 << 6)
+#define NX20P348X_INT2_SC_HVSNK   (1 << 5)
+#define NX20P348X_INT2_OV_HVSNK   (1 << 4)
+#define NX20P348X_INT2_RCP_HVSRC  (1 << 3)
+#define NX20P348X_INT2_SC_HVSRC   (1 << 2)
+#define NX20P348X_INT2_OC_HVSRC   (1 << 1)
+#define NX20P348X_INT2_OV_HVSRC   (1 << 0)
+
+struct ppc_drv;
+extern const struct ppc_drv nx20p348x_drv;
+
+/**
+ * Interrupt Handler for the NX20P348x.
+ *
+ * @param port: The Type-C port which triggered the interrupt.
+ */
+void nx20p348x_interrupt(int port);
+
+#endif /* defined(__CROS_EC_NX20P348X_H) */