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authorGwendal Grignou <gwendal@chromium.org>2018-03-12 10:58:21 -0700
committerchrome-bot <chrome-bot@chromium.org>2018-03-12 20:57:08 -0700
commit8e8d5a63e6dfc9dfc5faa6ff85e0f0b100806e78 (patch)
tree60701fa950aa1bc1d0a2b0f912205f8beb2d49f2 /driver
parentb8423e066922f70d65248abd8ad325177bfc615f (diff)
downloadchrome-ec-8e8d5a63e6dfc9dfc5faa6ff85e0f0b100806e78.tar.gz
driver: bma2x2: indent register definition
BUG=none BRANCH=none TEST=compile Change-Id: I9507cbe760f886acaa4c6b432cfd8482faeb4618 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/959387 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Diffstat (limited to 'driver')
-rw-r--r--driver/accel_bma2x2.c4
-rw-r--r--driver/accel_bma2x2.h189
2 files changed, 98 insertions, 95 deletions
diff --git a/driver/accel_bma2x2.c b/driver/accel_bma2x2.c
index b48ad864ff..b7af8c91df 100644
--- a/driver/accel_bma2x2.c
+++ b/driver/accel_bma2x2.c
@@ -119,7 +119,7 @@ static int set_range(const struct motion_sensor_t *s, int range, int rnd)
/* Find index for interface pair matching the specified range. */
index = find_param_index(range, rnd, ranges, ARRAY_SIZE(ranges));
- reg = BMA2x2_RANGE_SELECT_REG;
+ reg = BMA2x2_RANGE_SELECT_ADDR;
range_val = ranges[index].reg;
mutex_lock(s->mutex);
@@ -169,7 +169,7 @@ static int set_data_rate(const struct motion_sensor_t *s, int rate, int rnd)
index = find_param_index(rate, rnd, datarates, ARRAY_SIZE(datarates));
odr_val = datarates[index].reg;
- reg = BMA2x2_BW_REG;
+ reg = BMA2x2_BW_SELECT_ADDR;
mutex_lock(s->mutex);
diff --git a/driver/accel_bma2x2.h b/driver/accel_bma2x2.h
index 653b71257a..2ec8e8e0ff 100644
--- a/driver/accel_bma2x2.h
+++ b/driver/accel_bma2x2.h
@@ -38,124 +38,127 @@ extern const struct accelgyro_drv bma2x2_accel_drv;
* BMA250E
* BMA222E
*/
-#define BMA2x2_I2C_ADDR1 0x30
-#define BMA2x2_I2C_ADDR2 0x19
+#define BMA2x2_I2C_ADDR1 0x30
+#define BMA2x2_I2C_ADDR2 0x19
/* The following definition of I2C address is used for the following sensors
* BMC150
* BMC056
* BMC156
*/
-#define BMA2x2_I2C_ADDR3 0x10
-#define BMA2x2_I2C_ADDR4 0x11
+#define BMA2x2_I2C_ADDR3 0x10
+#define BMA2x2_I2C_ADDR4 0x11
/*** Chip-specific registers ***/
/* REGISTER ADDRESS DEFINITIONS */
-#define BMA2x2_EEP_OFFSET 0x16
-#define BMA2x2_IMAGE_BASE 0x38
-#define BMA2x2_IMAGE_LEN 22
-#define BMA2x2_CHIP_ID_ADDR 0x00
-#define BMA255_CHIP_ID_MAJOR 0xfa
+#define BMA2x2_EEP_OFFSET 0x16
+#define BMA2x2_IMAGE_BASE 0x38
+#define BMA2x2_IMAGE_LEN 22
+#define BMA2x2_CHIP_ID_ADDR 0x00
+#define BMA255_CHIP_ID_MAJOR 0xfa
/* DATA ADDRESS DEFINITIONS */
-#define BMA2x2_X_AXIS_LSB_ADDR 0x02
-#define BMA2x2_X_AXIS_MSB_ADDR 0x03
-#define BMA2x2_Y_AXIS_LSB_ADDR 0x04
-#define BMA2x2_Y_AXIS_MSB_ADDR 0x05
-#define BMA2x2_Z_AXIS_LSB_ADDR 0x06
-#define BMA2x2_Z_AXIS_MSB_ADDR 0x07
-#define BMA2x2_TEMP_ADDR 0x08
+#define BMA2x2_X_AXIS_LSB_ADDR 0x02
+#define BMA2x2_X_AXIS_MSB_ADDR 0x03
+#define BMA2x2_Y_AXIS_LSB_ADDR 0x04
+#define BMA2x2_Y_AXIS_MSB_ADDR 0x05
+#define BMA2x2_Z_AXIS_LSB_ADDR 0x06
+#define BMA2x2_Z_AXIS_MSB_ADDR 0x07
+#define BMA2x2_TEMP_ADDR 0x08
/* STATUS ADDRESS DEFINITIONS */
-#define BMA2x2_STAT1_ADDR 0x09
-#define BMA2x2_STAT2_ADDR 0x0A
-#define BMA2x2_STAT_TAP_SLOPE_ADDR 0x0B
-#define BMA2x2_STAT_ORIENT_HIGH_ADDR 0x0C
-#define BMA2x2_STAT_FIFO_ADDR 0x0E
-#define BMA2x2_RANGE_SELECT_ADDR 0x0F
-#define BMA2x2_BW_SELECT_ADDR 0x10
-#define BMA2x2_MODE_CTRL_ADDR 0x11
-#define BMA2x2_LOW_NOISE_CTRL_ADDR 0x12
-#define BMA2x2_DATA_CTRL_ADDR 0x13
-#define BMA2x2_RST_ADDR 0x14
-#define BMA2x2_CMD_SOFT_RESET 0xb6
+#define BMA2x2_STAT1_ADDR 0x09
+#define BMA2x2_STAT2_ADDR 0x0A
+#define BMA2x2_STAT_TAP_SLOPE_ADDR 0x0B
+#define BMA2x2_STAT_ORIENT_HIGH_ADDR 0x0C
+#define BMA2x2_STAT_FIFO_ADDR 0x0E
+#define BMA2x2_RANGE_SELECT_ADDR 0x0F
+#define BMA2x2_RANGE_SELECT_MSK 0x0F
+#define BMA2x2_RANGE_2G 3
+#define BMA2x2_RANGE_4G 5
+#define BMA2x2_RANGE_8G 8
+#define BMA2x2_RANGE_16G 12
+
+#define BMA2x2_BW_SELECT_ADDR 0x10
+#define BMA2x2_BW_MSK 0x1F
+#define BMA2x2_BW_7_81HZ 0x08 /* LowPass 7.81HZ */
+#define BMA2x2_BW_15_63HZ 0x09 /* LowPass 15.63HZ */
+#define BMA2x2_BW_31_25HZ 0x0A /* LowPass 31.25HZ */
+#define BMA2x2_BW_62_50HZ 0x0B /* LowPass 62.50HZ */
+#define BMA2x2_BW_125HZ 0x0C /* LowPass 125HZ */
+#define BMA2x2_BW_250HZ 0x0D /* LowPass 250HZ */
+#define BMA2x2_BW_500HZ 0x0E /* LowPass 500HZ */
+#define BMA2x2_BW_1000HZ 0x0F /* LowPass 1000HZ */
+
+#define BMA2x2_MODE_CTRL_ADDR 0x11
+#define BMA2x2_LOW_NOISE_CTRL_ADDR 0x12
+#define BMA2x2_DATA_CTRL_ADDR 0x13
+#define BMA2x2_RST_ADDR 0x14
+#define BMA2x2_CMD_SOFT_RESET 0xb6
/* INTERRUPT ADDRESS DEFINITIONS */
-#define BMA2x2_INTR_ENABLE1_ADDR 0x16
-#define BMA2x2_INTR_ENABLE2_ADDR 0x17
-#define BMA2x2_INTR_SLOW_NO_MOTION_ADDR 0x18
-#define BMA2x2_INTR1_PAD_SELECT_ADDR 0x19
-#define BMA2x2_INTR_DATA_SELECT_ADDR 0x1A
-#define BMA2x2_INTR2_PAD_SELECT_ADDR 0x1B
-#define BMA2x2_INTR_SOURCE_ADDR 0x1E
-#define BMA2x2_INTR_SET_ADDR 0x20
-#define BMA2x2_INTR_CTRL_ADDR 0x21
+#define BMA2x2_INTR_ENABLE1_ADDR 0x16
+#define BMA2x2_INTR_ENABLE2_ADDR 0x17
+#define BMA2x2_INTR_SLOW_NO_MOTION_ADDR 0x18
+#define BMA2x2_INTR1_PAD_SELECT_ADDR 0x19
+#define BMA2x2_INTR_DATA_SELECT_ADDR 0x1A
+#define BMA2x2_INTR2_PAD_SELECT_ADDR 0x1B
+#define BMA2x2_INTR_SOURCE_ADDR 0x1E
+#define BMA2x2_INTR_SET_ADDR 0x20
+#define BMA2x2_INTR_CTRL_ADDR 0x21
/* FEATURE ADDRESS DEFINITIONS */
-#define BMA2x2_LOW_DURN_ADDR 0x22
-#define BMA2x2_LOW_THRES_ADDR 0x23
-#define BMA2x2_LOW_HIGH_HYST_ADDR 0x24
-#define BMA2x2_HIGH_DURN_ADDR 0x25
-#define BMA2x2_HIGH_THRES_ADDR 0x26
-#define BMA2x2_SLOPE_DURN_ADDR 0x27
-#define BMA2x2_SLOPE_THRES_ADDR 0x28
-#define BMA2x2_SLOW_NO_MOTION_THRES_ADDR 0x29
-#define BMA2x2_TAP_PARAM_ADDR 0x2A
-#define BMA2x2_TAP_THRES_ADDR 0x2B
-#define BMA2x2_ORIENT_PARAM_ADDR 0x2C
-#define BMA2x2_THETA_BLOCK_ADDR 0x2D
-#define BMA2x2_THETA_FLAT_ADDR 0x2E
-#define BMA2x2_FLAT_HOLD_TIME_ADDR 0x2F
-#define BMA2x2_SELFTEST_ADDR 0x32
-#define BMA2x2_EEPROM_CTRL_ADDR 0x33
-#define BMA2x2_SERIAL_CTRL_ADDR 0x34
+#define BMA2x2_LOW_DURN_ADDR 0x22
+#define BMA2x2_LOW_THRES_ADDR 0x23
+#define BMA2x2_LOW_HIGH_HYST_ADDR 0x24
+#define BMA2x2_HIGH_DURN_ADDR 0x25
+#define BMA2x2_HIGH_THRES_ADDR 0x26
+#define BMA2x2_SLOPE_DURN_ADDR 0x27
+#define BMA2x2_SLOPE_THRES_ADDR 0x28
+#define BMA2x2_SLOW_NO_MOTION_THRES_ADDR 0x29
+#define BMA2x2_TAP_PARAM_ADDR 0x2A
+#define BMA2x2_TAP_THRES_ADDR 0x2B
+#define BMA2x2_ORIENT_PARAM_ADDR 0x2C
+#define BMA2x2_THETA_BLOCK_ADDR 0x2D
+#define BMA2x2_THETA_FLAT_ADDR 0x2E
+#define BMA2x2_FLAT_HOLD_TIME_ADDR 0x2F
+#define BMA2x2_SELFTEST_ADDR 0x32
+#define BMA2x2_EEPROM_CTRL_ADDR 0x33
+#define BMA2x2_SERIAL_CTRL_ADDR 0x34
/* OFFSET ADDRESS DEFINITIONS */
-#define BMA2x2_OFFSET_CTRL_ADDR 0x36
-#define BMA2x2_OFFSET_PARAMS_ADDR 0x37
-#define BMA2x2_OFFSET_X_AXIS_ADDR 0x38
-#define BMA2x2_OFFSET_Y_AXIS_ADDR 0x39
-#define BMA2x2_OFFSET_Z_AXIS_ADDR 0x3A
+#define BMA2x2_OFFSET_CTRL_ADDR 0x36
+#define BMA2x2_OFFSET_RESET 0x80
+#define BMA2x2_OFFSET_TRIGGER_OFF 5
+#define BMA2x2_OFFSET_TRIGGER_MASK (0x3 << BMA2x2_OFFSET_TRIGGER_OFF)
+#define BMA2x2_OFFSET_CAL_READY 0x10
+
+#define BMA2x2_OFC_SETTING_ADDR 0x37
+#define BMA2x2_OFC_TARGET_AXIS_OFF 1
+#define BMA2x2_OFC_TARGET_AXIS_LEN 2
+#define BMA2x2_OFC_TARGET_AXIS(_axis) \
+ (BMA2x2_OFC_TARGET_AXIS_LEN * (_axis) + BMA2x2_OFC_TARGET_AXIS_OFF)
+#define BMA2x2_OFC_TARGET_0G 0
+#define BMA2x2_OFC_TARGET_PLUS_1G 1
+#define BMA2x2_OFC_TARGET_MINUS_1G 2
+
+#define BMA2x2_OFFSET_X_AXIS_ADDR 0x38
+#define BMA2x2_OFFSET_Y_AXIS_ADDR 0x39
+#define BMA2x2_OFFSET_Z_AXIS_ADDR 0x3A
/* GP ADDRESS DEFINITIONS */
-#define BMA2x2_GP0_ADDR 0x3B
-#define BMA2x2_GP1_ADDR 0x3C
+#define BMA2x2_GP0_ADDR 0x3B
+#define BMA2x2_GP1_ADDR 0x3C
/* FIFO ADDRESS DEFINITIONS */
-#define BMA2x2_FIFO_MODE_ADDR 0x3E
-#define BMA2x2_FIFO_DATA_OUTPUT_ADDR 0x3F
-#define BMA2x2_FIFO_WML_TRIG 0x30
-
-/* RANGE */
-#define BMA2x2_RANGE_SELECT_POS 0
-#define BMA2x2_RANGE_SELECT_LEN 4
-#define BMA2x2_RANGE_SELECT_MSK 0x0F
-#define BMA2x2_RANGE_SELECT_REG BMA2x2_RANGE_SELECT_ADDR
-
-#define BMA2x2_RANGE_2G 3
-#define BMA2x2_RANGE_4G 5
-#define BMA2x2_RANGE_8G 8
-#define BMA2x2_RANGE_16G 12
+#define BMA2x2_FIFO_MODE_ADDR 0x3E
+#define BMA2x2_FIFO_DATA_OUTPUT_ADDR 0x3F
+#define BMA2x2_FIFO_WML_TRIG 0x30
/* Sensor resolution in number of bits. This sensor has fixed resolution. */
-#define BMA2x2_RESOLUTION 12
-
-/* BANDWIDTH */
-#define BMA2x2_BW_POS 0
-#define BMA2x2_BW_LEN 5
-#define BMA2x2_BW_MSK 0x1F
-#define BMA2x2_BW_REG BMA2x2_BW_SELECT_ADDR
-
-#define BMA2x2_BW_7_81HZ 0x08 /* LowPass 7.81HZ */
-#define BMA2x2_BW_15_63HZ 0x09 /* LowPass 15.63HZ */
-#define BMA2x2_BW_31_25HZ 0x0A /* LowPass 31.25HZ */
-#define BMA2x2_BW_62_50HZ 0x0B /* LowPass 62.50HZ */
-#define BMA2x2_BW_125HZ 0x0C /* LowPass 125HZ */
-#define BMA2x2_BW_250HZ 0x0D /* LowPass 250HZ */
-#define BMA2x2_BW_500HZ 0x0E /* LowPass 500HZ */
-#define BMA2x2_BW_1000HZ 0x0F /* LowPass 1000HZ */
+#define BMA2x2_RESOLUTION 12
/* Min and Max sampling frequency in mHz */
-#define BMA255_ACCEL_MIN_FREQ 7810
-#define BMA255_ACCEL_MAX_FREQ 1000000
+#define BMA255_ACCEL_MIN_FREQ 7810
+#define BMA255_ACCEL_MAX_FREQ 1000000
#endif /* __CROS_EC_ACCEL_BMA2x2_H */
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