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authorDenis Brockus <dbrockus@chromium.org>2019-07-16 15:10:11 -0600
committerCommit Bot <commit-bot@chromium.org>2019-08-23 00:12:33 +0000
commit6d39786d6a22fc355cd4d7eea384d254819c6a38 (patch)
tree1498442d7f20871ab76d7cfc50e843c4614f2616 /driver/ppc
parent5ef0acf4d369e48013da29e5f20f11bfab82155a (diff)
downloadchrome-ec-6d39786d6a22fc355cd4d7eea384d254819c6a38.tar.gz
Remove __7b, __8b and __7bf
The extentions were added to make the compiler perform most of the verification that the conversion was being done correctly to remove 8bit addressing as the standard I2C/SPI address type. Now that the compiler has verified the code, the extra extentions are being removed BUG=chromium:971296 BRANCH=none TEST=make buildall -j TEST=verify sensor functionality on arcada_ish Change-Id: I36894f8bb9daefb5b31b5e91577708f6f9af2a4f Signed-off-by: Denis Brockus <dbrockus@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1704792 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1767528 Reviewed-by: Edward Hill <ecgh@chromium.org> Commit-Queue: Edward Hill <ecgh@chromium.org> Tested-by: Edward Hill <ecgh@chromium.org>
Diffstat (limited to 'driver/ppc')
-rw-r--r--driver/ppc/nx20p348x.c8
-rw-r--r--driver/ppc/nx20p348x.h18
-rw-r--r--driver/ppc/sn5s330.c62
-rw-r--r--driver/ppc/sn5s330.h10
-rw-r--r--driver/ppc/syv682x.c12
-rw-r--r--driver/ppc/syv682x.h8
6 files changed, 59 insertions, 59 deletions
diff --git a/driver/ppc/nx20p348x.c b/driver/ppc/nx20p348x.c
index e8d2f52563..b0ba1f8b01 100644
--- a/driver/ppc/nx20p348x.c
+++ b/driver/ppc/nx20p348x.c
@@ -31,16 +31,16 @@ static uint8_t flags[CONFIG_USB_PD_PORT_COUNT];
static int read_reg(uint8_t port, int reg, int *regval)
{
- return i2c_read8__7bf(ppc_chips[port].i2c_port,
- ppc_chips[port].i2c_addr__7bf,
+ return i2c_read8(ppc_chips[port].i2c_port,
+ ppc_chips[port].i2c_addr_flags,
reg,
regval);
}
static int write_reg(uint8_t port, int reg, int regval)
{
- return i2c_write8__7bf(ppc_chips[port].i2c_port,
- ppc_chips[port].i2c_addr__7bf,
+ return i2c_write8(ppc_chips[port].i2c_port,
+ ppc_chips[port].i2c_addr_flags,
reg,
regval);
}
diff --git a/driver/ppc/nx20p348x.h b/driver/ppc/nx20p348x.h
index e34c5a2b56..86b33cf6bc 100644
--- a/driver/ppc/nx20p348x.h
+++ b/driver/ppc/nx20p348x.h
@@ -8,15 +8,15 @@
#ifndef __CROS_EC_NX20P348X_H
#define __CROS_EC_NX20P348X_H
-#define NX20P3483_ADDR0__7bf (0x70)
-#define NX20P3483_ADDR1__7bf (0x71)
-#define NX20P3483_ADDR2__7bf (0x72)
-#define NX20P3483_ADDR3__7bf (0x73)
-
-#define NX20P3481_ADDR0__7bf (0x74)
-#define NX20P3481_ADDR1__7bf (0x75)
-#define NX20P3481_ADDR2__7bf (0x76)
-#define NX20P3481_ADDR3__7bf (0x77)
+#define NX20P3483_ADDR0_FLAGS 0x70
+#define NX20P3483_ADDR1_FLAGS 0x71
+#define NX20P3483_ADDR2_FLAGS 0x72
+#define NX20P3483_ADDR3_FLAGS 0x73
+
+#define NX20P3481_ADDR0_FLAGS 0x74
+#define NX20P3481_ADDR1_FLAGS 0x75
+#define NX20P3481_ADDR2_FLAGS 0x76
+#define NX20P3481_ADDR3_FLAGS 0x77
/*
* This PPC hard-codes the over voltage protect of Vbus at 6.8V in dead-battery
diff --git a/driver/ppc/sn5s330.c b/driver/ppc/sn5s330.c
index 13834a8bf3..85db762148 100644
--- a/driver/ppc/sn5s330.c
+++ b/driver/ppc/sn5s330.c
@@ -31,16 +31,16 @@ static int source_enabled[CONFIG_USB_PD_PORT_COUNT];
static int read_reg(uint8_t port, int reg, int *regval)
{
- return i2c_read8__7bf(ppc_chips[port].i2c_port,
- ppc_chips[port].i2c_addr__7bf,
+ return i2c_read8(ppc_chips[port].i2c_port,
+ ppc_chips[port].i2c_addr_flags,
reg,
regval);
}
static int write_reg(uint8_t port, int reg, int regval)
{
- return i2c_write8__7bf(ppc_chips[port].i2c_port,
- ppc_chips[port].i2c_addr__7bf,
+ return i2c_write8(ppc_chips[port].i2c_port,
+ ppc_chips[port].i2c_addr_flags,
reg,
regval);
}
@@ -78,12 +78,12 @@ static int sn5s330_dump(int port)
int i;
int data;
const int i2c_port = ppc_chips[port].i2c_port;
- const uint16_t i2c_addr__7bf = ppc_chips[port].i2c_addr__7bf;
+ const uint16_t i2c_addr_flags = ppc_chips[port].i2c_addr_flags;
/* Flush after every set otherwise console buffer may get full. */
for (i = SN5S330_FUNC_SET1; i <= SN5S330_FUNC_SET12; i++) {
- i2c_read8__7bf(i2c_port, i2c_addr__7bf, i, &data);
+ i2c_read8(i2c_port, i2c_addr_flags, i, &data);
ccprintf("FUNC_SET%d [%02Xh] = 0x%02x\n",
i - SN5S330_FUNC_SET1 + 1,
i,
@@ -93,7 +93,7 @@ static int sn5s330_dump(int port)
cflush();
for (i = SN5S330_INT_STATUS_REG1; i <= SN5S330_INT_STATUS_REG4; i++) {
- i2c_read8__7bf(i2c_port, i2c_addr__7bf, i, &data);
+ i2c_read8(i2c_port, i2c_addr_flags, i, &data);
ccprintf("INT_STATUS_REG%d [%02Xh] = 0x%02x\n",
i - SN5S330_INT_STATUS_REG1 + 1,
i,
@@ -104,7 +104,7 @@ static int sn5s330_dump(int port)
for (i = SN5S330_INT_TRIP_RISE_REG1; i <= SN5S330_INT_TRIP_RISE_REG3;
i++) {
- i2c_read8__7bf(i2c_port, i2c_addr__7bf, i, &data);
+ i2c_read8(i2c_port, i2c_addr_flags, i, &data);
ccprintf("INT_TRIP_RISE_REG%d [%02Xh] = 0x%02x\n",
i - SN5S330_INT_TRIP_RISE_REG1 + 1,
i,
@@ -115,7 +115,7 @@ static int sn5s330_dump(int port)
for (i = SN5S330_INT_TRIP_FALL_REG1; i <= SN5S330_INT_TRIP_FALL_REG3;
i++) {
- i2c_read8__7bf(i2c_port, i2c_addr__7bf, i, &data);
+ i2c_read8(i2c_port, i2c_addr_flags, i, &data);
ccprintf("INT_TRIP_FALL_REG%d [%02Xh] = 0x%02x\n",
i - SN5S330_INT_TRIP_FALL_REG1 + 1,
i,
@@ -126,7 +126,7 @@ static int sn5s330_dump(int port)
for (i = SN5S330_INT_MASK_RISE_REG1; i <= SN5S330_INT_MASK_RISE_REG3;
i++) {
- i2c_read8__7bf(i2c_port, i2c_addr__7bf, i, &data);
+ i2c_read8(i2c_port, i2c_addr_flags, i, &data);
ccprintf("INT_MASK_RISE_REG%d [%02Xh] = 0x%02x\n",
i - SN5S330_INT_MASK_RISE_REG1 + 1,
i,
@@ -137,7 +137,7 @@ static int sn5s330_dump(int port)
for (i = SN5S330_INT_MASK_FALL_REG1; i <= SN5S330_INT_MASK_FALL_REG3;
i++) {
- i2c_read8__7bf(i2c_port, i2c_addr__7bf, i, &data);
+ i2c_read8(i2c_port, i2c_addr_flags, i, &data);
ccprintf("INT_MASK_FALL_REG%d [%02Xh] = 0x%02x\n",
i - SN5S330_INT_MASK_FALL_REG1 + 1,
i,
@@ -184,7 +184,7 @@ static int sn5s330_init(int port)
int retries;
int reg;
const int i2c_port = ppc_chips[port].i2c_port;
- const uint16_t i2c_addr__7bf = ppc_chips[port].i2c_addr__7bf;
+ const uint16_t i2c_addr_flags = ppc_chips[port].i2c_addr_flags;
#ifdef CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT
/* Set the sourcing current limit value. */
@@ -211,7 +211,7 @@ static int sn5s330_init(int port)
*/
retries = 0;
do {
- status = i2c_write8__7bf(i2c_port, i2c_addr__7bf,
+ status = i2c_write8(i2c_port, i2c_addr_flags,
SN5S330_FUNC_SET1, regval);
if (status) {
CPRINTS("ppc p%d: Failed to set FUNC_SET1! Retrying..",
@@ -225,7 +225,7 @@ static int sn5s330_init(int port)
/* Set Vbus OVP threshold to ~22.325V. */
regval = 0x37;
- status = i2c_write8__7bf(i2c_port, i2c_addr__7bf,
+ status = i2c_write8(i2c_port, i2c_addr_flags,
SN5S330_FUNC_SET5, regval);
if (status) {
CPRINTS("ppc p%d: Failed to set FUNC_SET5!", port);
@@ -233,7 +233,7 @@ static int sn5s330_init(int port)
}
/* Set Vbus UVP threshold to ~2.75V. */
- status = i2c_read8__7bf(i2c_port, i2c_addr__7bf,
+ status = i2c_read8(i2c_port, i2c_addr_flags,
SN5S330_FUNC_SET6, &regval);
if (status) {
CPRINTS("ppc p%d: Failed to read FUNC_SET6!", port);
@@ -241,7 +241,7 @@ static int sn5s330_init(int port)
}
regval &= ~0x3F;
regval |= 1;
- status = i2c_write8__7bf(i2c_port, i2c_addr__7bf,
+ status = i2c_write8(i2c_port, i2c_addr_flags,
SN5S330_FUNC_SET6, regval);
if (status) {
CPRINTS("ppc p%d: Failed to write FUNC_SET6!", port);
@@ -250,7 +250,7 @@ static int sn5s330_init(int port)
/* Enable SBU Fets and set PP2 current limit to ~3A. */
regval = SN5S330_SBU_EN | 0x8;
- status = i2c_write8__7bf(i2c_port, i2c_addr__7bf,
+ status = i2c_write8(i2c_port, i2c_addr_flags,
SN5S330_FUNC_SET2, regval);
if (status) {
CPRINTS("ppc p%d: Failed to set FUNC_SET2!", port);
@@ -270,7 +270,7 @@ static int sn5s330_init(int port)
* low voltage protection).
*/
regval = SN5S330_OVP_EN_CC | SN5S330_PP2_CONFIG | SN5S330_CONFIG_UVP;
- status = i2c_write8__7bf(i2c_port, i2c_addr__7bf,
+ status = i2c_write8(i2c_port, i2c_addr_flags,
SN5S330_FUNC_SET9, regval);
if (status) {
CPRINTS("ppc p%d: Failed to set FUNC_SET9!", port);
@@ -279,7 +279,7 @@ static int sn5s330_init(int port)
/* Set analog current limit delay to 200 us for both PP1 & PP2. */
regval = (PPX_ILIM_DEGLITCH_0_US_200 << 3) | PPX_ILIM_DEGLITCH_0_US_200;
- status = i2c_write8__7bf(i2c_port, i2c_addr__7bf,
+ status = i2c_write8(i2c_port, i2c_addr_flags,
SN5S330_FUNC_SET11, regval);
if (status) {
CPRINTS("ppc p%d: Failed to set FUNC_SET11", port);
@@ -293,7 +293,7 @@ static int sn5s330_init(int port)
* reset default (20 us).
*/
regval = 0;
- status = i2c_read8__7bf(i2c_port, i2c_addr__7bf,
+ status = i2c_read8(i2c_port, i2c_addr_flags,
SN5S330_FUNC_SET8, &regval);
if (status) {
CPRINTS("ppc p%d: Failed to read FUNC_SET8!", port);
@@ -301,7 +301,7 @@ static int sn5s330_init(int port)
}
regval &= ~SN5S330_VCONN_DEGLITCH_MASK;
regval |= SN5S330_VCONN_DEGLITCH_640_US;
- status = i2c_write8__7bf(i2c_port, i2c_addr__7bf,
+ status = i2c_write8(i2c_port, i2c_addr_flags,
SN5S330_FUNC_SET8, regval);
if (status) {
CPRINTS("ppc p%d: Failed to set FUNC_SET8!", port);
@@ -354,7 +354,7 @@ static int sn5s330_init(int port)
* is checked below.
*/
regval = SN5S330_DIG_RES | SN5S330_VSAFE0V_MASK;
- status = i2c_write8__7bf(i2c_port, i2c_addr__7bf,
+ status = i2c_write8(i2c_port, i2c_addr_flags,
SN5S330_INT_STATUS_REG4, regval);
if (status) {
CPRINTS("ppc p%d: Failed to write INT_STATUS_REG4!", port);
@@ -372,14 +372,14 @@ static int sn5s330_init(int port)
*/
regval = ~SN5S330_ILIM_PP1_MASK;
- status = i2c_write8__7bf(i2c_port, i2c_addr__7bf,
+ status = i2c_write8(i2c_port, i2c_addr_flags,
SN5S330_INT_MASK_RISE_REG1, regval);
if (status) {
CPRINTS("ppc p%d: Failed to write INT_MASK_RISE1!", port);
return status;
}
- status = i2c_write8__7bf(i2c_port, i2c_addr__7bf,
+ status = i2c_write8(i2c_port, i2c_addr_flags,
SN5S330_INT_MASK_FALL_REG1, regval);
if (status) {
CPRINTS("ppc p%d: Failed to write INT_MASK_FALL1!", port);
@@ -387,14 +387,14 @@ static int sn5s330_init(int port)
}
/* Now mask all the other interrupts. */
- status = i2c_write8__7bf(i2c_port, i2c_addr__7bf,
+ status = i2c_write8(i2c_port, i2c_addr_flags,
SN5S330_INT_MASK_RISE_REG2, 0xFF);
if (status) {
CPRINTS("ppc p%d: Failed to write INT_MASK_RISE2!", port);
return status;
}
- status = i2c_write8__7bf(i2c_port, i2c_addr__7bf,
+ status = i2c_write8(i2c_port, i2c_addr_flags,
SN5S330_INT_MASK_FALL_REG2, 0xFF);
if (status) {
CPRINTS("ppc p%d: Failed to write INT_MASK_FALL2!", port);
@@ -408,14 +408,14 @@ static int sn5s330_init(int port)
regval = 0xFF;
#endif /* CONFIG_USB_PD_VBUS_DETECT_PPC && CONFIG_USB_CHARGER */
- status = i2c_write8__7bf(i2c_port, i2c_addr__7bf,
+ status = i2c_write8(i2c_port, i2c_addr_flags,
SN5S330_INT_MASK_RISE_REG3, regval);
if (status) {
CPRINTS("ppc p%d: Failed to write INT_MASK_RISE3!", port);
return status;
}
- status = i2c_write8__7bf(i2c_port, i2c_addr__7bf,
+ status = i2c_write8(i2c_port, i2c_addr_flags,
SN5S330_INT_MASK_FALL_REG3, regval);
if (status) {
CPRINTS("ppc p%d: Failed to write INT_MASK_FALL3!", port);
@@ -426,7 +426,7 @@ static int sn5s330_init(int port)
for (reg = SN5S330_INT_TRIP_RISE_REG1;
reg <= SN5S330_INT_TRIP_FALL_REG3;
reg++) {
- status = i2c_write8__7bf(i2c_port, i2c_addr__7bf,
+ status = i2c_write8(i2c_port, i2c_addr_flags,
reg, 0xFF);
if (status) {
CPRINTS("ppc p%d: Failed to write reg 0x%2x!", port);
@@ -439,7 +439,7 @@ static int sn5s330_init(int port)
* For PP2, check to see if we booted in dead battery mode. If we
* booted in dead battery mode, the PP2 FET will already be enabled.
*/
- status = i2c_read8__7bf(i2c_port, i2c_addr__7bf,
+ status = i2c_read8(i2c_port, i2c_addr_flags,
SN5S330_INT_STATUS_REG4, &regval);
if (status) {
CPRINTS("ppc p%d: Failed to read INT_STATUS_REG4!", port);
@@ -451,7 +451,7 @@ static int sn5s330_init(int port)
* Clear the bit by writing 1 and keep vSafe0V_MASK
* unchanged.
*/
- i2c_write8__7bf(i2c_port, i2c_addr__7bf,
+ i2c_write8(i2c_port, i2c_addr_flags,
SN5S330_INT_STATUS_REG4, regval);
/* Turn on PP2 FET. */
diff --git a/driver/ppc/sn5s330.h b/driver/ppc/sn5s330.h
index a153b9d25a..263452a5a2 100644
--- a/driver/ppc/sn5s330.h
+++ b/driver/ppc/sn5s330.h
@@ -12,7 +12,7 @@
struct sn5s330_config {
uint8_t i2c_port;
- uint8_t i2c_addr__7bf;
+ uint8_t i2c_addr_flags;
};
extern const struct sn5s330_config sn5s330_chips[];
@@ -25,10 +25,10 @@ enum sn5s330_pp_idx {
SN5S330_PP_COUNT,
};
-#define SN5S330_ADDR0__7bf (0x40)
-#define SN5S330_ADDR1__7bf (0x41)
-#define SN5S330_ADDR2__7bf (0x42)
-#define SN5S330_ADDR3__7bf (0x43)
+#define SN5S330_ADDR0_FLAGS 0x40
+#define SN5S330_ADDR1_FLAGS 0x41
+#define SN5S330_ADDR2_FLAGS 0x42
+#define SN5S330_ADDR3_FLAGS 0x43
#define SN5S330_FUNC_SET1 0x50
#define SN5S330_FUNC_SET2 0x51
diff --git a/driver/ppc/syv682x.c b/driver/ppc/syv682x.c
index a8f5c146bb..5f80dd3d90 100644
--- a/driver/ppc/syv682x.c
+++ b/driver/ppc/syv682x.c
@@ -23,16 +23,16 @@ static uint8_t flags[CONFIG_USB_PD_PORT_COUNT];
static int read_reg(uint8_t port, int reg, int *regval)
{
- return i2c_read8__7bf(ppc_chips[port].i2c_port,
- ppc_chips[port].i2c_addr__7bf,
+ return i2c_read8(ppc_chips[port].i2c_port,
+ ppc_chips[port].i2c_addr_flags,
reg,
regval);
}
static int write_reg(uint8_t port, int reg, int regval)
{
- return i2c_write8__7bf(ppc_chips[port].i2c_port,
- ppc_chips[port].i2c_addr__7bf,
+ return i2c_write8(ppc_chips[port].i2c_port,
+ ppc_chips[port].i2c_addr_flags,
reg,
regval);
}
@@ -258,11 +258,11 @@ static int syv682x_dump(int port)
int data;
int rv;
const int i2c_port = ppc_chips[port].i2c_port;
- const int i2c_addr__7bf = ppc_chips[port].i2c_addr__7bf;
+ const int i2c_addr_flags = ppc_chips[port].i2c_addr_flags;
for (reg_addr = SYV682X_STATUS_REG; reg_addr <= SYV682X_CONTROL_4_REG;
reg_addr++) {
- rv = i2c_read8__7bf(i2c_port, i2c_addr__7bf, reg_addr, &data);
+ rv = i2c_read8(i2c_port, i2c_addr_flags, reg_addr, &data);
if (rv)
ccprintf("ppc_syv682[p%d]: Failed to read reg 0x%02x\n",
port, reg_addr);
diff --git a/driver/ppc/syv682x.h b/driver/ppc/syv682x.h
index f355fe1cf9..4a76659f41 100644
--- a/driver/ppc/syv682x.h
+++ b/driver/ppc/syv682x.h
@@ -9,10 +9,10 @@
#define __CROS_EC_SYV682X_H
/* I2C addresses */
-#define SYV682X_ADDR0__7bf 0x40
-#define SYV682X_ADDR1__7bf 0x41
-#define SYV682X_ADDR2__7bf 0x42
-#define SYV682x_ADDR3__7bf 0x43
+#define SYV682X_ADDR0_FLAGS 0x40
+#define SYV682X_ADDR1_FLAGS 0x41
+#define SYV682X_ADDR2_FLAGS 0x42
+#define SYV682x_ADDR3_FLAGS 0x43
/* SYV682x register addresses */
#define SYV682X_STATUS_REG 0x00