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| author | Shawn Nematbakhsh <shawnn@chromium.org> | 2015-09-05 17:27:37 -0700 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2015-09-16 14:49:32 -0700 |
| commit | 558c465165acf494905fa59c822c7190b4646899 (patch) | |
| tree | a20a512da9d8aed29cb46d99b8df0b8bb0ab5714 /core | |
| parent | d58e54730c03290296df5bb65cb84264e4b2facc (diff) | |
| download | chrome-ec-558c465165acf494905fa59c822c7190b4646899.tar.gz | |
cleanup: Remove CDRAM / CODERAM CONFIGs
CDRAM / CODERAM configs were previously used for chips which copied code
from external SPI to program memory prior to execution, and were used
inconsistently between npcx and mec1322.
These CONFIGs are now completely redundant given new configs like
CONFIG_MAPPED_STORAGE_BASE and CONFIG_EXTERNAL_STORAGE.
BRANCH=None
BUG=chrome-os-partner:23796
TEST=With entire patch series, on both Samus and Glados:
- Verify 'version' EC console command is correct
- Verify 'flashrom -p ec -r read.bin' reads back EC image
- Verify software sync correctly flashes both EC and PD RW images
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I0e054ab4c939f9dcf54abee8e5ebd9b2e42fe9c4
Reviewed-on: https://chromium-review.googlesource.com/297804
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Diffstat (limited to 'core')
| -rw-r--r-- | core/cortex-m/ec.lds.S | 19 |
1 files changed, 6 insertions, 13 deletions
diff --git a/core/cortex-m/ec.lds.S b/core/cortex-m/ec.lds.S index 6e5eefba32..7fcf6f0adc 100644 --- a/core/cortex-m/ec.lds.S +++ b/core/cortex-m/ec.lds.S @@ -31,18 +31,11 @@ MEMORY #endif FLASH (rx) : ORIGIN = FW_OFF(SECTION), LENGTH = FW_SIZE(SECTION) IRAM (rw) : ORIGIN = CONFIG_RAM_BASE, LENGTH = CONFIG_RAM_SIZE -#ifdef CONFIG_CODERAM_ARCH -#ifdef CONFIG_MAPPED_STORAGE - /* Geometry constants have non-standard meaning for npcx */ +#ifdef CONFIG_EXTERNAL_STORAGE CDRAM (rx) : \ - ORIGIN = CONFIG_CDRAM_BASE, \ - LENGTH = CONFIG_CDRAM_SIZE -#else /* CONFIG_MAPPED_STORAGE */ - CDRAM (rx) : \ - ORIGIN = CONFIG_CDRAM_BASE + FW_MEM_OFF(SECTION), \ + ORIGIN = CONFIG_PROGRAM_MEMORY_BASE + FW_MEM_OFF(SECTION), \ LENGTH = FW_SIZE(SECTION) -#endif /* CONFIG_MAPPED_STORAGE */ -#endif /* CONFIG_CODERAM_ARCH */ +#endif /* CONFIG_EXTERNAL_STORAGE */ #ifdef RSA_PUBLIC_KEY_SIZE PSTATE(r) : \ ORIGIN = FW_OFF(SECTION) + FW_SIZE(SECTION), \ @@ -85,7 +78,7 @@ SECTIONS #endif OUTDIR/core/CORE/init.o (.text) *(.text*) -#ifdef CONFIG_CODERAM_ARCH +#ifdef CONFIG_EXTERNAL_STORAGE __flash_lpfw_start = .; /* Entering deep idle FW for better power consumption */ KEEP(*(.lowpower_ram)) @@ -200,7 +193,7 @@ SECTIONS KEEP(*(.google)) #endif . = ALIGN(4); -#ifdef CONFIG_CODERAM_ARCH +#ifdef CONFIG_EXTERNAL_STORAGE } > CDRAM AT > FLASH #else } > FLASH @@ -229,7 +222,7 @@ SECTIONS . = ALIGN(4); __bss_end = .; } > IRAM -#ifdef CONFIG_CODERAM_ARCH +#ifdef CONFIG_EXTERNAL_STORAGE .data : AT(LOADADDR(.rodata) + SIZEOF(.rodata)) { #else .data : AT(ADDR(.rodata) + SIZEOF(.rodata)) { |