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| author | Tzung-Bi Shih <tzungbi@chromium.org> | 2020-03-20 12:06:16 +0800 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2020-05-19 08:55:30 +0000 |
| commit | cb352aa0d6986828bafb2c1b530ed6c93e6f2089 (patch) | |
| tree | ff8eb8bb22dd3abdd4e5eea095a99d45c1739ac5 /core | |
| parent | 6faa7b37201ca4ca9e6ba988db893d57dd059652 (diff) | |
| download | chrome-ec-cb352aa0d6986828bafb2c1b530ed6c93e6f2089.tar.gz | |
core/riscv-rv32i: guard more IT83XX chip specific items
Guards IT83XX chip specific:
- E-flash signature.
- BRAM (Battery-backed SRAM).
Moves IT83XX_GCTRL_EIDSR to IT83XX chip specific.
BRANCH=none
BUG=b:151897847
TEST=1. make BOARD=asurada
2. flash_ec --board=asurada --image build/asurada/ec.bin
3. (EC console)> version
Signed-off-by: Tzung-Bi Shih <tzungbi@chromium.org>
Change-Id: I05ea628c6b745136043b9505c98204381bd7a0ea
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2114950
Reviewed-by: Eric Yilun Lin <yllin@chromium.org>
Reviewed-by: Dino Li <Dino.Li@ite.com.tw>
Diffstat (limited to 'core')
| -rw-r--r-- | core/riscv-rv32i/init.S | 17 |
1 files changed, 7 insertions, 10 deletions
diff --git a/core/riscv-rv32i/init.S b/core/riscv-rv32i/init.S index dedd7a644f..844a49d7c3 100644 --- a/core/riscv-rv32i/init.S +++ b/core/riscv-rv32i/init.S @@ -7,13 +7,6 @@ #include "config.h" -/* - * ILM/DLM size register. - * bit[3-0] ILM size: - * 7: 512K byte (default setting), 8: 1M byte - */ -#define IT83XX_GCTRL_EIDSR 0xf02031 - .macro vector name .set \name\()_handler, unhandled_ec_irq .weak \name\()_handler @@ -36,6 +29,7 @@ __startup: __irq: j __irq_isr /* interrupts / exceptions */ +#ifdef CHIP_FAMILY_IT8XXX2 /* * E-flash signature used to enable specific function after power-on reset. * (HW mechanism) @@ -69,6 +63,7 @@ eflash_sig: .byte 0xB4 /* flag of signature */ .byte 0x85, 0x12, 0x5A, 0x5A, 0xAA, 0xAA, 0x55, 0x55 /* flags: internal oscillator + implicit location */ +#endif /* CHIP_FAMILY_IT8XXX2 */ .align 2 __ec_intc: @@ -290,7 +285,7 @@ __reset: /* The M-mode handles interrupt/exception */ csrwi mideleg, 0 csrwi medeleg, 0 -#ifdef IT83XX_CHIP_FLASH_SIZE_1MB +#if defined(IT83XX_CHIP_FLASH_SIZE_1MB) && defined(CHIP_FAMILY_IT8XXX2) /* ILM size is 1M bytes */ la t0, IT83XX_GCTRL_EIDSR lb t1, 0(t0) @@ -318,8 +313,10 @@ data_loop: /* store the content of t5 (ra after reset) into "ec_reset_lp" */ la t0, ec_reset_lp sw t5, 0(t0) - /* clear BRAM if it is not valid */ - jal chip_bram_valid +#ifdef CHIP_FAMILY_IT8XXX2 + /* clear BRAM if it is not valid */ + jal chip_bram_valid +#endif /* Jump to C routine */ jal main /* That should not return. If it does, loop forever. */ |