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| author | Jes B. Klinke <jbk@chromium.org> | 2023-02-01 20:54:42 -0800 |
|---|---|---|
| committer | Chromeos LUCI <chromeos-scoped@luci-project-accounts.iam.gserviceaccount.com> | 2023-02-03 19:41:43 +0000 |
| commit | c69c1be3c13c6f8dd96d5203570ce7cb7f40e42b (patch) | |
| tree | f5d700ba30c1cc4e57aa85716bb5270402f03aa5 /core | |
| parent | 609fdf79e88dd9304ac243fa9449e1455bf4561c (diff) | |
| download | chrome-ec-c69c1be3c13c6f8dd96d5203570ce7cb7f40e42b.tar.gz | |
core/cortex-m: Allow copying vector table into SRAM
The STM32F0 family (Cortex-M0) makes use of copying the vector table
into SRAM, and the core/cortex-m0/ec.lds.S declares a data section for
this purpose, put as the very first SRAM address in order to satisfy
alignmen requirements. For other Cortex-M0 chips besides the STM32F0,
the linker section exists, but is empty as no data is declared to go
into it. (Any particular board could decide to declare space, copy the
vector table, and modify the VTOR register, if they wanted, though.)
This CL copies the linker section declaration from cortex-m0/ into
cortex-m/, such that boards using other kinds of Cortex-M can also
optionally copy their vector table into SRAM.
BUG=b:266832220
TEST=./util/compare_build.sh -b {discovery,munna}
Change-Id: I6222f360f52ec4928327860fd1bf78860dfba120
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4216264
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Commit-Queue: Jes Klinke <jbk@chromium.org>
Tested-by: Jes Klinke <jbk@chromium.org>
Diffstat (limited to 'core')
| -rw-r--r-- | core/cortex-m/ec.lds.S | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/core/cortex-m/ec.lds.S b/core/cortex-m/ec.lds.S index b6dc1dd7df..b370d1acf0 100644 --- a/core/cortex-m/ec.lds.S +++ b/core/cortex-m/ec.lds.S @@ -389,6 +389,22 @@ SECTIONS #define INIT_ROM_LMA ORIGIN(ROM_RESIDENT_VMA) #endif + /* + * This SRAM section is not used by common/ or chip/stm32/, but + * available if particular boards want to move the vector table + * into SRAM for performance or mutability. + */ + .vtable : { + /* + * Vector table must be at the base of SRAM. The vector + * table section contains a RAM copy of the vector table used on + * STM chips for relocating the vector table. + */ + . = ALIGN(8); + *(.bss.vector_table) + . = ALIGN(8); + } > IRAM + #ifdef CONFIG_PRESERVE_LOGS .preserve_logs(NOLOAD) : { . = ALIGN(8); |