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| author | CHLin <CHLIN56@nuvoton.com> | 2017-11-07 10:50:16 +0800 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2017-11-09 21:46:07 -0800 |
| commit | 16f4c65daf528de399bf622d0aefcadc19238544 (patch) | |
| tree | 142aa240b3a6fe0fecc39355a32fbe7c37e79353 /core | |
| parent | d972385836212826d9179f4532e33e41b85f185f (diff) | |
| download | chrome-ec-16f4c65daf528de399bf622d0aefcadc19238544.tar.gz | |
npcx: fixed the assembly code of deep idle bypass
The original assembly code of deep sleep bypass will cause build error
if both CONFIG_LOW_POWER_IDLE and CONFIG_LTO are defined when buildiing
board glkrvp/zoombini. This CL fixed it by change the bypass assembly code
from:
asm ("push {r0-r5}\n"
"ldr r0, =0x100A8000\n"
"wfi\n"
"ldm r0, {r0-r5}\n"
"pop {r0-r5}\n"
"isb\n"
);
to:
asm ("push {r0-r5}\n"
"wfi\n"
"ldm %0, {r0-r5}\n"
"pop {r0-r5}\n"
"isb\n" :: "r" (0x100A8000)
);
BRANCH=none
BUG=none
TEST=No build errors for "make buildall".
TEST=build zoombini/glkrvp with CONFIG_LOW_POWER_IDLE and CONFIG_LTO,
no build errors.
TEST=build npcx7_evb/npcx_evb and do stress test for deep idle->wakeup
on EVB, no symptom observed.
Change-Id: I90b13b4baf418e3f4b3234d4811e3978b6436aac
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
Signed-off-by: CHLin <CHLIN56@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/756535
Commit-Ready: CH Lin <chlin56@nuvoton.com>
Tested-by: CH Lin <chlin56@nuvoton.com>
Diffstat (limited to 'core')
| -rw-r--r-- | core/cortex-m/task.c | 5 |
1 files changed, 2 insertions, 3 deletions
diff --git a/core/cortex-m/task.c b/core/cortex-m/task.c index 67785d4366..bab5310245 100644 --- a/core/cortex-m/task.c +++ b/core/cortex-m/task.c @@ -90,12 +90,11 @@ void __idle(void) asm ( "cpsid i\n" /* Disable interrupt */ "push {r0-r5}\n" /* Save needed registers */ - "ldr r0, =0x100A8000\n" /* Set r0 to a valid RAM addr */ "wfi\n" /* Wait for int to enter idle */ - "ldm r0, {r0-r5}\n" /* Add a delay after WFI */ + "ldm %0, {r0-r5}\n" /* Add a delay after WFI */ "pop {r0-r5}\n" /* Restore regs before enabling ints */ "isb\n" /* Flush the cpu pipeline */ - "cpsie i\n" /* Enable interrupts */ + "cpsie i\n" :: "r" (0x100A8000) /* Enable interrupts */ ); #else /* |