diff options
author | Vincent Palatin <vpalatin@chromium.org> | 2014-03-03 11:51:37 -0800 |
---|---|---|
committer | chrome-internal-fetch <chrome-internal-fetch@google.com> | 2014-03-06 21:32:57 +0000 |
commit | 6ab4ad5f95ea86156d0e47b806c7a6bcfbae67d8 (patch) | |
tree | ecc0aa5da00777b478ce3ebdc53ed07eac4ec25c /core | |
parent | 75f59a47ec90bfd4f21bfbab7536c4ad13847595 (diff) | |
download | chrome-ec-6ab4ad5f95ea86156d0e47b806c7a6bcfbae67d8.tar.gz |
Move CLZ emulation to common code
Move the CLZ instruction emulation C code to the common directory, so it
can be reused for all CPU cores missing a CLZ instruction (e.g. CortexM0).
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=none
TEST=run EC console on STM32F072B Discovery board with Cortex-M0 core,
and pass all available unit-tests on target.
Change-Id: Ief56cac7430fcb0fbced8a8925250c89cbd0bcfc
Reviewed-on: https://chromium-review.googlesource.com/188981
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Diffstat (limited to 'core')
-rw-r--r-- | core/nds32/config_core.h | 5 | ||||
-rw-r--r-- | core/nds32/cpu.c | 39 |
2 files changed, 5 insertions, 39 deletions
diff --git a/core/nds32/config_core.h b/core/nds32/config_core.h index d7a25d27da..750d47b016 100644 --- a/core/nds32/config_core.h +++ b/core/nds32/config_core.h @@ -10,6 +10,11 @@ #define BFD_ARCH nds32 #define BFD_FORMAT "elf32-nds32le" +/* + * The Andestar v3m architecture has no CLZ instruction (contrary to v3), + * so let's use the software implementation. + */ +#define CONFIG_SOFTWARE_CLZ /* * Force the compiler to use a proper relocation when accessing an external diff --git a/core/nds32/cpu.c b/core/nds32/cpu.c index e4dc5db94c..545e930eca 100644 --- a/core/nds32/cpu.c +++ b/core/nds32/cpu.c @@ -11,42 +11,3 @@ void cpu_init(void) { /* DLM initialization is done in init.S */ } - -/** - * Count leading zeros - * - * @param x non null integer. - * @return the number of leading 0-bits in x, - * starting at the most significant bit position. - * - * The Andestar v3m architecture has no CLZ instruction (contrary to v3), - * so let's use the software implementation. - */ -int __clzsi2(int x) -{ - int r = 0; - - if (!x) - return 32; - if (!(x & 0xffff0000u)) { - x <<= 16; - r += 16; - } - if (!(x & 0xff000000u)) { - x <<= 8; - r += 8; - } - if (!(x & 0xf0000000u)) { - x <<= 4; - r += 4; - } - if (!(x & 0xc0000000u)) { - x <<= 2; - r += 2; - } - if (!(x & 0x80000000u)) { - x <<= 1; - r += 1; - } - return r; -} |