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| author | Mary Ruthven <mruthven@chromium.org> | 2021-11-09 19:51:21 -0600 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2021-11-18 04:53:09 +0000 |
| commit | 6ca7a0b7f0055333ef09945d0dedb7cc8ea9ef50 (patch) | |
| tree | 0063305a6927869f36ffcf4761840071331118b2 /core | |
| parent | 4076cecbaf563e010610a20b9fe2870754996f03 (diff) | |
| download | chrome-ec-6ca7a0b7f0055333ef09945d0dedb7cc8ea9ef50.tar.gz | |
Revert "npcx: bypass for CSAE issue if CONFIG_LOW_POWER_IDLE is disabled"
This reverts commit ebe3caeb69aeaa9144701415decc3e6647df01cd.
BUG=b:200823466
TEST=make buildall -j
Change-Id: I53b5c29ab306e4b3c9abfaad7d78db46dc62c72a
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3273452
Reviewed-by: Vadim Sukhomlinov <sukhomlinov@chromium.org>
Diffstat (limited to 'core')
| -rw-r--r-- | core/cortex-m/task.c | 12 |
1 files changed, 0 insertions, 12 deletions
diff --git a/core/cortex-m/task.c b/core/cortex-m/task.c index 07219d3fbb..1def5e0aa5 100644 --- a/core/cortex-m/task.c +++ b/core/cortex-m/task.c @@ -68,18 +68,6 @@ void __idle(void) { while (1) { #ifdef CHIP_NPCX - - /* - * Using host access to make sure M4 core clock will - * return when the eSPI accesses the Host modules if - * CSAE bit is set. Please notice this symptom only - * occurs at npcx5. - */ -#if defined(CHIP_FAMILY_NPCX5) && defined(CONFIG_HOSTCMD_ESPI) - /* Enable Host access wakeup */ - SET_BIT(NPCX_WKEN(MIWU_TABLE_0, MIWU_GROUP_5), 6); -#endif - /* * TODO (ML): A interrupt that occurs shortly before entering * idle mode starts getting services while the Core transitions |