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| author | Daisuke Nojiri <dnojiri@chromium.org> | 2021-03-11 13:17:35 -0800 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2021-03-18 22:49:28 +0000 |
| commit | 3f940a5e45a8db587efff0721d4038c59cb702e3 (patch) | |
| tree | 1bb1f8412800d1ccc2166c5262b64fd20757d6c8 /core/riscv-rv32i | |
| parent | 6a6d35734c355b24d0fd0dd9d2e941652c2a4772 (diff) | |
| download | chrome-ec-3f940a5e45a8db587efff0721d4038c59cb702e3.tar.gz | |
ctn730: Make reset pulse 15 usec
This patch changes the reset pulse from 1 msec to 15 usec. The
datasheet says the minimum reset pulse length is 10 usec.
This is better not to be a sleep especially if it's long
(e.g. ~1 ms) since the PCHG state machine may try to access the
I2C bus, which is held low by ctn730 during reset.
BUG=b:173235954
BRANCH=trogdor
TEST=Stylus connect, disconnect, charge events are triggered as
expected.
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Change-Id: Ibe611b32bd0f88ad875b24c38bbea577d8d4ec10
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2770505
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Diffstat (limited to 'core/riscv-rv32i')
0 files changed, 0 insertions, 0 deletions