diff options
| author | Dino Li <dino.li@ite.com.tw> | 2015-10-28 21:39:54 +0800 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2015-11-01 19:45:58 -0800 |
| commit | 2ea7b194d928950db1aed87097975a8ffb9df2ac (patch) | |
| tree | e0ea13ac6acf404c8298fe2544fe3ae2fb32c21d /core/nds32 | |
| parent | ba63ef190e5818e1221baaafd44fbc65aa10209b (diff) | |
| download | chrome-ec-2ea7b194d928950db1aed87097975a8ffb9df2ac.tar.gz | |
nds32: fix interrupt
1. To enable INT_PRI (hardware interrupt priority level 0~3)
register, bit0@INT_CTRL = 0.
2. GIE need to be enabled before UART is initialized.
[symptom]
To define CONFIG_RWSIG / CONFIG_RSA / CONFIG_SHA256, then power on:
after RW image is verified, firmware stuck in uart_flush_output().
Signed-off-by: Dino Li <dino.li@ite.com.tw>
BRANCH=none
BUG=none
TEST=1. bit0@INT_CTRL = 0.
2. The RW image is verified and jump to image RW.
Change-Id: I393a3d5f87ea257885b872c91bfce43aecbaea8b
Reviewed-on: https://chromium-review.googlesource.com/309400
Commit-Ready: Dino Li <dino.li@ite.com.tw>
Tested-by: Dino Li <dino.li@ite.com.tw>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Diffstat (limited to 'core/nds32')
| -rw-r--r-- | core/nds32/cpu.c | 3 | ||||
| -rw-r--r-- | core/nds32/task.c | 19 |
2 files changed, 22 insertions, 0 deletions
diff --git a/core/nds32/cpu.c b/core/nds32/cpu.c index bf49a58b2e..7a8a043656 100644 --- a/core/nds32/cpu.c +++ b/core/nds32/cpu.c @@ -18,4 +18,7 @@ void cpu_init(void) if (image_type > CONFIG_RW_MEM_OFF) /* Interrupt Vector Table Base Address, in 64k Byte unit */ IT83XX_GCTRL_IVTBAR = (CONFIG_RW_MEM_OFF >> 16) & 0xFF; + + /* Global interrupt enable */ + asm volatile ("setgie.e"); } diff --git a/core/nds32/task.c b/core/nds32/task.c index a7a3bc6688..79880e059d 100644 --- a/core/nds32/task.c +++ b/core/nds32/task.c @@ -494,6 +494,19 @@ static void set_int_priority(uint32_t val) asm volatile ("mtsr %0, $INT_PRI" : : "r"(val)); } +uint32_t get_int_ctrl(void) +{ + uint32_t ret; + + asm volatile ("mfsr %0, $INT_CTRL" : "=r"(ret)); + return ret; +} + +void set_int_ctrl(uint32_t val) +{ + asm volatile ("mtsr %0, $INT_CTRL" : : "r"(val)); +} + void task_enable_all_tasks(void) { /* Mark all tasks are ready to run. */ @@ -550,6 +563,12 @@ static void ivic_init_irqs(void) chip_init_irqs(); /* + * bit0 @ INT_CTRL = 0, + * Interrupts still keep programmable priority level. + */ + set_int_ctrl((get_int_ctrl() & ~(1 << 0))); + + /* * Re-enable global interrupts in case they're disabled. On a reboot, * they're already enabled; if we've jumped here from another image, * they're not. |