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| author | michael_chen <michael5_chen@pegatroncorp.com> | 2018-10-09 12:58:44 +0800 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2018-10-09 05:10:46 -0700 |
| commit | fa06e1f393c1a9c644b8731b8fde17af10dd9907 (patch) | |
| tree | 0afc6af18a12769a519180a0709387d4a3864443 /core/cortex-m | |
| parent | d5a657ab1d77dce1e54d283b3556acf940d10426 (diff) | |
| download | chrome-ec-fa06e1f393c1a9c644b8731b8fde17af10dd9907.tar.gz | |
rammus: Fix power leakage
Modify PMIC and GPIO setting to fix power leakage.
Dependent on EE request:
1. Init PMIC Discharge control register.
1.1. Discharge control register 1 (0x3C) = 0x00.
1.2. Discharge control register 2 (0x3D) = 0x55.
1.3. Discharge control register 3 (0x3E) = 0x44.
1.4. Discharge control register 4 (0x3F) = 0x04.
2. Remove gpio "TP_INT_CONN" GPIO_PULL_UP configuration.
BUG=b:117194355
BRANCH=ToT
TEST=Manual
EE measure power and check it is improve.
Change-Id: I8b0e5ff479fee0ebcc26e9e57073ec6b5fc8868f
Signed-off-by: michael_chen <michael5_chen@pegatroncorp.com>
Reviewed-on: https://chromium-review.googlesource.com/1253369
Commit-Ready: michael chen <michael5_chen@pegatroncorp.com>
Tested-by: michael chen <michael5_chen@pegatroncorp.com>
Reviewed-by: Zhuohao Lee <zhuohao@chromium.org>
Diffstat (limited to 'core/cortex-m')
0 files changed, 0 insertions, 0 deletions