diff options
| author | Vincent Palatin <vpalatin@chromium.org> | 2014-03-01 10:20:47 -0800 |
|---|---|---|
| committer | chrome-internal-fetch <chrome-internal-fetch@google.com> | 2014-03-11 05:52:41 +0000 |
| commit | 0f73a129b42acfcad843203b602fbbcc8894c614 (patch) | |
| tree | 9531fae7a8d9c3290973fe5b5ee47e57cd485546 /core/cortex-m0/cpu.h | |
| parent | 7aab81edce830e15134b52256ad3186e08951b10 (diff) | |
| download | chrome-ec-0f73a129b42acfcad843203b602fbbcc8894c614.tar.gz | |
Add Cortex-M0 core support
The Cortex-M0 core is based on ARMv6-M instruction set rather than
ARMv7-M as Cortex-M3 and M4.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=none
TEST=run console on STM32F072,
and pass all available unit-tests on target.
Change-Id: I9bdf6637132ba4a3e739d388580a72b4c84e930e
Reviewed-on: https://chromium-review.googlesource.com/188982
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Diffstat (limited to 'core/cortex-m0/cpu.h')
| -rw-r--r-- | core/cortex-m0/cpu.h | 38 |
1 files changed, 38 insertions, 0 deletions
diff --git a/core/cortex-m0/cpu.h b/core/cortex-m0/cpu.h new file mode 100644 index 0000000000..8b874d9688 --- /dev/null +++ b/core/cortex-m0/cpu.h @@ -0,0 +1,38 @@ +/* Copyright (c) 2014 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + * + * Registers map and definitions for Cortex-M0 processor + */ + +#ifndef __CPU_H +#define __CPU_H + +#include <stdint.h> + +/* Macro to access 32-bit registers */ +#define CPUREG(addr) (*(volatile uint32_t*)(addr)) + +/* Nested Vectored Interrupt Controller */ +#define CPU_NVIC_EN(x) CPUREG(0xe000e100) +#define CPU_NVIC_DIS(x) CPUREG(0xe000e180) +#define CPU_NVIC_UNPEND(x) CPUREG(0xe000e280) +#define CPU_NVIC_ISPR(x) CPUREG(0xe000e200) +#define CPU_NVIC_PRI(x) CPUREG(0xe000e400) + +/* System Control Block */ + +/* SCB AIRCR : Application interrupt and reset control register */ +#define CPU_NVIC_APINT CPUREG(0xe000ed0c) +/* SCB SCR : System Control Register */ +#define CPU_SCB_SYSCTRL CPUREG(0xe000ed10) +#define CPU_NVIC_CCR CPUREG(0xe000ed14) +#define CPU_NVIC_SHCSR2 CPUREG(0xe000ed1c) +#define CPU_NVIC_SHCSR3 CPUREG(0xe000ed20) + +#define CPU_NVIC_CCR_UNALIGN_TRAP (1 << 3) + +/* Set up the cpu to detect faults */ +void cpu_init(void); + +#endif /* __CPU_H */ |