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| author | Peter Marheine <pmarheine@chromium.org> | 2020-03-16 16:26:07 +1100 |
|---|---|---|
| committer | Chromeos LUCI <chromeos-scoped@luci-project-accounts.iam.gserviceaccount.com> | 2022-03-28 18:17:11 +0000 |
| commit | 91f79e5855bf48bfc82d99076aee3797d15fe9f0 (patch) | |
| tree | c0fe1649b135113c9f15099c99f5373ee34c7487 /core/cortex-m/cpu.h | |
| parent | cf96131c91213628e56ed82527b83d20177609bf (diff) | |
| download | chrome-ec-91f79e5855bf48bfc82d99076aee3797d15fe9f0.tar.gz | |
Rename Cortex-M MMFS to CFSR
Taken as as 32-bit register, ARM call the register at 0xe000ed28 CFSR;
the Configurable Fault Status Register. MMFS is the low byte of this
value, so it's misleading to refer to the whole 32-bit value as MMFS;
instead call it CFSR to make it clear that the value we store
encompasses the MMFSR, BFSR and UFSR.
BUG=b:218982018
BRANCH=None
TEST=make buildall
Change-Id: Ifd62e0a6f27a2e6ddfa509b84c389d960347ff85
Signed-off-by: Peter Marheine <pmarheine@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2104807
Reviewed-by: Keith Short <keithshort@chromium.org>
(cherry picked from commit 124b2a8654b1bca281277b581fb79daeb1bdadde)
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3457944
Diffstat (limited to 'core/cortex-m/cpu.h')
| -rw-r--r-- | core/cortex-m/cpu.h | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/core/cortex-m/cpu.h b/core/cortex-m/cpu.h index a6029e2e7e..32a4205018 100644 --- a/core/cortex-m/cpu.h +++ b/core/cortex-m/cpu.h @@ -31,15 +31,15 @@ #define CPU_NVIC_CCR CPUREG(0xe000ed14) #define CPU_NVIC_SHCSR CPUREG(0xe000ed24) -#define CPU_NVIC_MMFS CPUREG(0xe000ed28) +#define CPU_NVIC_CFSR CPUREG(0xe000ed28) #define CPU_NVIC_HFSR CPUREG(0xe000ed2c) #define CPU_NVIC_DFSR CPUREG(0xe000ed30) #define CPU_NVIC_MFAR CPUREG(0xe000ed34) #define CPU_NVIC_BFAR CPUREG(0xe000ed38) enum { - CPU_NVIC_MMFS_BFARVALID = 1 << 15, - CPU_NVIC_MMFS_MFARVALID = 1 << 7, + CPU_NVIC_CFSR_BFARVALID = 1 << 15, + CPU_NVIC_CFSR_MFARVALID = 1 << 7, CPU_NVIC_CCR_ICACHE = 1 << 17, CPU_NVIC_CCR_DCACHE = 1 << 16, |