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| author | Vincent Palatin <vpalatin@chromium.org> | 2018-04-27 08:15:57 +0200 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2018-06-04 10:09:42 -0700 |
| commit | edbfb3a43b6c4e1dd28f6d00a59896cae198f68b (patch) | |
| tree | e2fe1d6f4e5da6b0fc1b96853ed3a4819959d982 /core/cortex-m/cpu.h | |
| parent | a6c9a3cd2194d555b926d4a0789827b5dd341b9d (diff) | |
| download | chrome-ec-edbfb3a43b6c4e1dd28f6d00a59896cae198f68b.tar.gz | |
cortex-m: add D-cache support
Add support to enable the architectural D-cache on ARMv7-M CPU
supporting it.
Update the MPU code in order to be able to declare an 'uncached' RAM
region (e.g. to store the DMA buffer).
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=poppy
BUG=b:78535052, b:75068419
TEST=with the following CL, on ZerbleBarn, boot and capture a finger
image.
Change-Id: I275445e7c0b558cedc3e7d6fc6840ff9b4b76285
Reviewed-on: https://chromium-review.googlesource.com/1032776
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
Diffstat (limited to 'core/cortex-m/cpu.h')
| -rw-r--r-- | core/cortex-m/cpu.h | 9 |
1 files changed, 7 insertions, 2 deletions
diff --git a/core/cortex-m/cpu.h b/core/cortex-m/cpu.h index f4400a0444..a6029e2e7e 100644 --- a/core/cortex-m/cpu.h +++ b/core/cortex-m/cpu.h @@ -60,10 +60,15 @@ enum { #define CPU_SCB_CCSELR CPUREG(0xe000ed84) #define CPU_SCB_ICIALLU CPUREG(0xe000ef50) #define CPU_SCB_DCISW CPUREG(0xe000ef60) +#define CPU_SCB_DCCISW CPUREG(0xe000ef74) /* Set up the cpu to detect faults */ void cpu_init(void); -/* Enable the CPU instruction cache if it is not already enabled */ -void cpu_enable_icache(void); +/* Enable the CPU I-cache and D-cache if they are not already enabled */ +void cpu_enable_caches(void); +/* Invalidate the D-cache */ +void cpu_invalidate_dcache(void); +/* Clean and Invalidate the D-cache to the Point of Coherency */ +void cpu_clean_invalidate_dcache(void); #endif /* __CROS_EC_CPU_H */ |