coil: cleanup commentsstabilize-rust-13720.B-cr50_stab

BUG=b:175244613
TEST=make buildall -j

Change-Id: Icbd143b072fdd5df3b67d7e5a09ee6c01a77f6b9
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2622889
Reviewed-by: Namyoon Woo <namyoon@chromium.org>

4 files changed, 11 insertions, 11 deletions

diff --git a/common/ccd_config.c b/common/ccd_config.c
index 91232df295..f83789a26f 100644
--- a/common/ccd_config.c
+++ b/common/ccd_config.c
@@ -1459,7 +1459,7 @@ static enum vendor_cmd_rc ccd_vendor(struct vendor_cmd_params *p)
 	p->in_size++;
 
 	/*
-	 * Move response up for the master to see it in the right
+	 * Move response up for the controller to see it in the right
 	 * place in the response buffer.  We have to do this because the
 	 * first byte of the buffer on input was the subcommand, so we
 	 * passed buffer + 1 in the handler call above.
diff --git a/common/i2c_controller.c b/common/i2c_controller.c
index ac65483185..60d48e8b68 100644
--- a/common/i2c_controller.c
+++ b/common/i2c_controller.c
@@ -805,14 +805,14 @@ int i2c_unwedge(int port)
 
 	/*
 	 * If clock is low, wait for a while in case of clock stretched
-	 * by a slave.
+	 * by a peripheral.
 	 */
 	if (!i2c_raw_get_scl(port)) {
 		for (i = 0;; i++) {
 			if (i >= UNWEDGE_SCL_ATTEMPTS) {
 				/*
-				 * If we get here, a slave is holding the clock
-				 * low and there is nothing we can do.
+				 * If we get here, a peripheral is holding the
+				 * clock low and there is nothing we can do.
 				 */
 				CPRINTS("I2C%d unwedge failed, "
 					"SCL is held low", port);
@@ -837,9 +837,9 @@ int i2c_unwedge(int port)
 		udelay(I2C_BITBANG_DELAY_US);
 
 		/*
-		 * Clock through the problem by clocking out 9 bits. If slave
-		 * releases the SDA line, then we can stop clocking bits and
-		 * send a STOP.
+		 * Clock through the problem by clocking out 9 bits. If the
+		 * peripheral releases the SDA line, then we can stop clocking
+		 * bits and send a STOP.
 		 */
 		for (j = 0; j < 9; j++) {
 			if (i2c_raw_get_sda(port))
diff --git a/common/new_nvmem.c b/common/new_nvmem.c
index b7bb2b1c11..d3bfcb40b4 100644
--- a/common/new_nvmem.c
+++ b/common/new_nvmem.c
@@ -692,7 +692,7 @@ static enum ec_error_list set_first_page_header(void)
 	rv = write_to_flash(fph, &ph, sizeof(ph));
 
 	if (rv == EC_SUCCESS) {
-		/* Make sure master page tracker is ready. */
+		/* Make sure the controller page tracker is ready. */
 		memset(&controller_at, 0, sizeof(controller_at));
 		controller_at.mt.data_offset = ph.data_offset;
 		controller_at.mt.ph = fph;
diff --git a/common/tpm_registers.c b/common/tpm_registers.c
index b821df7f9a..185cadf97f 100644
--- a/common/tpm_registers.c
+++ b/common/tpm_registers.c
@@ -5,8 +5,8 @@
 
 /*
  * This implements the register interface for the TPM SPI Hardware Protocol.
- * The master puts or gets between 1 and 64 bytes to a register designated by a
- * 24-bit address. There is no provision for error reporting at this level.
+ * The controller puts or gets between 1 and 64 bytes to a register designated
+ * by a24-bit address. There is no provision for error reporting at this level.
  */
 
 #include "byteorder.h"
@@ -495,7 +495,7 @@ static void fifo_reg_read(uint8_t *dest, uint32_t data_size)
 		tpm_sts |= 63 << burst_count_shift;
 	} else {
 		/*
-		 * Tell the master how much there is to read in the next
+		 * Tell the controller how much there is to read in the next
 		 * burst.
 		 */
 		tpm_sts |= MIN(tpm_.fifo_write_index -