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| author | Vijay Hiremath <vijay.p.hiremath@intel.com> | 2019-09-04 15:59:45 -0700 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2019-09-05 23:04:33 +0000 |
| commit | df7ecbc55f4b7d67174a14db9dc781789f07ac60 (patch) | |
| tree | 1a96ae424a2a2400fc81b9d0b313f8ef435aa0e0 /common/usbc/usb_prl_sm.c | |
| parent | b47a5ca84dfd6b75a4cd76837d81cac0345c000f (diff) | |
| download | chrome-ec-df7ecbc55f4b7d67174a14db9dc781789f07ac60.tar.gz | |
power: Add power sequencing logic for Tigerlake chipset
Power sequencing logic for Tigerlake is same as Icelake hence
reusing the Icelake code.
BUG=b:140508849
BRANCH=none
TEST=tglrvp can boot to S0
Change-Id: Id218422146e5549aa5b246ddbcaedd8e442e376b
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1785685
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Diffstat (limited to 'common/usbc/usb_prl_sm.c')
0 files changed, 0 insertions, 0 deletions