cleanup: Rename image geometry CONFIGs

Rename image geometry configs with a uniform naming scheme to make their
purposes more clear.

CONFIG_RO_MEM_OFF (was CONFIG_FW_RO_OFF) - RO image offset in program memory
CONFIG_RO_STORAGE_OFF (was CONFIG_RO_SPI_OFF) - RO image offset on storage
CONFIG_RO_SIZE (was CONFIG_FW_RO_SIZE) - Size of RO image

CONFIG_RW_MEM_OFF (was CONFIG_FW_RW_OFF) - RW image offset in program memory
CONFIG_RW_STORAGE_OFF (was CONFIG_RW_SPI_OFF) - RW image offset on storage
CONFIG_RW_SIZE (was CONFIG_FW_RW_SIZE) - Size of RW image

CONFIG_WP_OFF (was CONFIG_FW_WP_RO_OFF) - Offset of WP region on storage
CONFIG_WP_SIZE (was CONFIG_FW_WP_RO_SIZE) - Size of WP region on storage

BUG=chrome-os-partner:39741,chrome-os-partner:23796
TEST=Set date / version strings to constants then `make buildall -j`.
Verify that each ec.bin image is identical pre- and post-change.
BRANCH=None

Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I6ea0a4e456dae71c266fa917a309b9f6fa4b50cd
Reviewed-on: https://chromium-review.googlesource.com/270189
Reviewed-by: Anton Staaf <robotboy@chromium.org>

21 files changed, 127 insertions, 127 deletions

diff --git a/chip/g/config_std_flash.h b/chip/g/config_std_flash.h
index cee332fad2..86df29c4e4 100644
--- a/chip/g/config_std_flash.h
+++ b/chip/g/config_std_flash.h
@@ -7,7 +7,7 @@
 #define __CROS_EC_CONFIG_STD_FLASH_H
 
 /* RO firmware must start at beginning of flash */
-#define CONFIG_FW_RO_OFF		0
+#define CONFIG_RO_MEM_OFF		0
 
 /*
  * The EC uses the one bank of flash to emulate a SPI-like write protect
@@ -16,17 +16,17 @@
 #define CONFIG_FW_PSTATE_SIZE		CONFIG_FLASH_BANK_SIZE
 
 /* PSTATE immediately follows RO, in the first half of flash */
-#define CONFIG_FW_RO_SIZE		(CONFIG_FW_IMAGE_SIZE		\
+#define CONFIG_RO_SIZE			(CONFIG_FW_IMAGE_SIZE		\
 					 - CONFIG_FW_PSTATE_SIZE)
-#define CONFIG_FW_PSTATE_OFF		CONFIG_FW_RO_SIZE
+#define CONFIG_FW_PSTATE_OFF		CONFIG_RO_SIZE
 #define CONFIG_FLASH_SIZE		CONFIG_FLASH_PHYSICAL_SIZE
 
 /* RW firmware is one firmware image offset from the start */
-#define CONFIG_FW_RW_OFF		CONFIG_FW_IMAGE_SIZE
-#define CONFIG_FW_RW_SIZE		CONFIG_FW_IMAGE_SIZE
+#define CONFIG_RW_MEM_OFF		CONFIG_FW_IMAGE_SIZE
+#define CONFIG_RW_SIZE			CONFIG_FW_IMAGE_SIZE
 
 /* TODO(crosbug.com/p/23796): why 2 sets of configs with the same numbers? */
-#define CONFIG_FW_WP_RO_OFF		CONFIG_FW_RO_OFF
-#define CONFIG_FW_WP_RO_SIZE		CONFIG_FW_RO_SIZE
+#define CONFIG_WP_OFF			CONFIG_RO_MEM_OFF
+#define CONFIG_WP_SIZE			CONFIG_RO_SIZE
 
 #endif	/* __CROS_EC_CONFIG_STD_FLASH_H */
diff --git a/chip/host/config_chip.h b/chip/host/config_chip.h
index a83fa778cf..df84143883 100644
--- a/chip/host/config_chip.h
+++ b/chip/host/config_chip.h
@@ -26,18 +26,18 @@ extern char __host_flash[CONFIG_FLASH_PHYSICAL_SIZE];
 /* Size of one firmware image in flash */
 #define CONFIG_FW_IMAGE_SIZE    (64 * 1024)
 
-#define CONFIG_FW_RO_OFF        0
-#define CONFIG_FW_RO_SIZE       (CONFIG_FW_IMAGE_SIZE - CONFIG_FW_PSTATE_SIZE)
-#define CONFIG_FW_RW_OFF        CONFIG_FW_IMAGE_SIZE
-#define CONFIG_FW_RW_SIZE       CONFIG_FW_IMAGE_SIZE
-#define CONFIG_FW_WP_RO_OFF     CONFIG_FW_RO_OFF
-#define CONFIG_FW_WP_RO_SIZE    CONFIG_FW_IMAGE_SIZE
+#define CONFIG_RO_MEM_OFF       0
+#define CONFIG_RO_SIZE          (CONFIG_FW_IMAGE_SIZE - CONFIG_FW_PSTATE_SIZE)
+#define CONFIG_RW_MEM_OFF       CONFIG_FW_IMAGE_SIZE
+#define CONFIG_RW_SIZE          CONFIG_FW_IMAGE_SIZE
+#define CONFIG_WP_OFF           CONFIG_RO_MEM_OFF
+#define CONFIG_WP_SIZE          CONFIG_FW_IMAGE_SIZE
 
 /*
  * Put this after RO to give RW more space and make RO write protect region
  * contiguous.
  */
-#define CONFIG_FW_PSTATE_OFF    CONFIG_FW_RO_SIZE
+#define CONFIG_FW_PSTATE_OFF    CONFIG_RO_SIZE
 #define CONFIG_FW_PSTATE_SIZE   CONFIG_FLASH_BANK_SIZE
 
 /* Maximum number of deferrable functions */
diff --git a/chip/host/system.c b/chip/host/system.c
index 6e1d1c36bf..e9de6b1214 100644
--- a/chip/host/system.c
+++ b/chip/host/system.c
@@ -261,8 +261,8 @@ void system_pre_init(void)
 		system_set_reset_flags(load_reset_flags());
 	}
 
-	*(uintptr_t *)(__host_flash + CONFIG_FW_RO_OFF + 4) =
+	*(uintptr_t *)(__host_flash + CONFIG_RO_MEM_OFF + 4) =
 		(uintptr_t)__ro_jump_resetvec;
-	*(uintptr_t *)(__host_flash + CONFIG_FW_RW_OFF + 4) =
+	*(uintptr_t *)(__host_flash + CONFIG_RW_MEM_OFF + 4) =
 		(uintptr_t)__rw_jump_resetvec;
 }
diff --git a/chip/it83xx/config_chip.h b/chip/it83xx/config_chip.h
index d7b13d1480..5caf50562b 100644
--- a/chip/it83xx/config_chip.h
+++ b/chip/it83xx/config_chip.h
@@ -62,7 +62,7 @@
 #endif
 
 /* RO firmware must start at beginning of flash */
-#define CONFIG_FW_RO_OFF		0
+#define CONFIG_RO_MEM_OFF		0
 
 /*
  * The EC uses the one bank of flash to emulate a SPI-like write protect
@@ -71,18 +71,18 @@
 #define CONFIG_FW_PSTATE_SIZE		CONFIG_FLASH_BANK_SIZE
 
 /* PSTATE immediately follows RO, in the first half of flash */
-#define CONFIG_FW_RO_SIZE		(CONFIG_FW_IMAGE_SIZE		\
+#define CONFIG_RO_SIZE			(CONFIG_FW_IMAGE_SIZE		\
 					 - CONFIG_FW_PSTATE_SIZE)
-#define CONFIG_FW_PSTATE_OFF		CONFIG_FW_RO_SIZE
+#define CONFIG_FW_PSTATE_OFF		CONFIG_RO_SIZE
 #define CONFIG_FLASH_SIZE		CONFIG_FLASH_PHYSICAL_SIZE
 
 /* RW firmware is one firmware image offset from the start */
-#define CONFIG_FW_RW_OFF		CONFIG_FW_IMAGE_SIZE
-#define CONFIG_FW_RW_SIZE		CONFIG_FW_IMAGE_SIZE
+#define CONFIG_RW_MEM_OFF		CONFIG_FW_IMAGE_SIZE
+#define CONFIG_RW_SIZE			CONFIG_FW_IMAGE_SIZE
 
 /* TODO: why 2 sets of configs with the same numbers? */
-#define CONFIG_FW_WP_RO_OFF		CONFIG_FW_RO_OFF
-#define CONFIG_FW_WP_RO_SIZE		CONFIG_FW_RO_SIZE
+#define CONFIG_WP_OFF			CONFIG_RO_MEM_OFF
+#define CONFIG_WP_SIZE			CONFIG_RO_SIZE
 
 /****************************************************************************/
 /* Customize the build */
diff --git a/chip/lm4/config_chip.h b/chip/lm4/config_chip.h
index 535b677701..433510d460 100644
--- a/chip/lm4/config_chip.h
+++ b/chip/lm4/config_chip.h
@@ -75,7 +75,7 @@
 #endif
 
 /* RO firmware must start at beginning of flash */
-#define CONFIG_FW_RO_OFF		0
+#define CONFIG_RO_MEM_OFF		0
 
 /*
  * The EC uses the one bank of flash to emulate a SPI-like write protect
@@ -84,18 +84,18 @@
 #define CONFIG_FW_PSTATE_SIZE		CONFIG_FLASH_BANK_SIZE
 
 /* PSTATE immediately follows RO, in the first half of flash */
-#define CONFIG_FW_RO_SIZE		(CONFIG_FW_IMAGE_SIZE		\
+#define CONFIG_RO_SIZE			(CONFIG_FW_IMAGE_SIZE		\
 					 - CONFIG_FW_PSTATE_SIZE)
-#define CONFIG_FW_PSTATE_OFF		CONFIG_FW_RO_SIZE
+#define CONFIG_FW_PSTATE_OFF		CONFIG_RO_SIZE
 #define CONFIG_FLASH_SIZE		CONFIG_FLASH_PHYSICAL_SIZE
 
 /* RW firmware is one firmware image offset from the start */
-#define CONFIG_FW_RW_OFF		CONFIG_FW_IMAGE_SIZE
-#define CONFIG_FW_RW_SIZE		CONFIG_FW_IMAGE_SIZE
+#define CONFIG_RW_MEM_OFF		CONFIG_FW_IMAGE_SIZE
+#define CONFIG_RW_SIZE			CONFIG_FW_IMAGE_SIZE
 
 /* TODO(crosbug.com/p/23796): why 2 sets of configs with the same numbers? */
-#define CONFIG_FW_WP_RO_OFF		CONFIG_FW_RO_OFF
-#define CONFIG_FW_WP_RO_SIZE		CONFIG_FW_RO_SIZE
+#define CONFIG_WP_OFF			CONFIG_RO_MEM_OFF
+#define CONFIG_WP_SIZE			CONFIG_RO_SIZE
 
 /****************************************************************************/
 /* Lock the boot configuration to prevent brickage. */
diff --git a/chip/mec1322/config_chip.h b/chip/mec1322/config_chip.h
index 3accdfdf63..ffdf0e56d4 100644
--- a/chip/mec1322/config_chip.h
+++ b/chip/mec1322/config_chip.h
@@ -110,20 +110,20 @@
 #endif
 
 /* RO/RW firmware must be after Loader code */
-#define CONFIG_FW_RO_OFF		CONFIG_FW_LOADER_SIZE
+#define CONFIG_RO_MEM_OFF		CONFIG_FW_LOADER_SIZE
 
-#define CONFIG_FW_RO_SIZE		CONFIG_FW_IMAGE_SIZE
+#define CONFIG_RO_SIZE			CONFIG_FW_IMAGE_SIZE
 #define CONFIG_FLASH_SIZE		CONFIG_FLASH_PHYSICAL_SIZE
 
 #define  CONFIG_FW_INCLUDE_RO
-#define CONFIG_FW_RW_OFF		CONFIG_FW_RO_OFF
-#define CONFIG_FW_RW_SIZE		CONFIG_FW_RO_SIZE
+#define CONFIG_RW_MEM_OFF		CONFIG_RO_MEM_OFF
+#define CONFIG_RW_SIZE			CONFIG_RO_SIZE
 
 /* Write protect Loader and RO Image */
-#define CONFIG_FW_WP_RO_OFF		CONFIG_FW_LOADER_OFF
+#define CONFIG_WP_OFF			CONFIG_FW_LOADER_OFF
 /* Write protect 128k section of 256k physical flash
 which contains Loader and RO Images */
-#define CONFIG_FW_WP_RO_SIZE		(CONFIG_FLASH_PHYSICAL_SIZE >> 1)
+#define CONFIG_WP_SIZE			(CONFIG_FLASH_PHYSICAL_SIZE >> 1)
 /****************************************************************************/
 /* SPI Flash Memory Mapping */
 
@@ -132,12 +132,12 @@ which contains Loader and RO Images */
 #define CONFIG_FLASH_BASE_SPI	(CONFIG_SPI_FLASH_SIZE - (0x40000))
 
 #define CONFIG_RO_WP_SPI_OFF		0x20000
-#define CONFIG_RO_SPI_OFF		0x20000
-#define CONFIG_RW_SPI_OFF		0
+#define CONFIG_RO_STORAGE_OFF		0x20000
+#define CONFIG_RW_STORAGE_OFF		0
 #define CONFIG_RO_IMAGE_FLASHADDR	(CONFIG_FLASH_BASE_SPI +	\
-						CONFIG_RO_SPI_OFF)
+						CONFIG_RO_STORAGE_OFF)
 #define CONFIG_RW_IMAGE_FLASHADDR	(CONFIG_FLASH_BASE_SPI +	\
-						CONFIG_RW_SPI_OFF)
+						CONFIG_RW_STORAGE_OFF)
 /* Memory Lcation shared between lfw and RO/RWimage */
 #define SHARED_RAM_LFW_RORW		(CONFIG_MEC_SRAM_BASE_START + \
 						(CONFIG_LOADER_IMAGE_SIZE - 4))
diff --git a/chip/mec1322/flash.c b/chip/mec1322/flash.c
index e9c752e917..78beb72429 100644
--- a/chip/mec1322/flash.c
+++ b/chip/mec1322/flash.c
@@ -123,8 +123,8 @@ int flash_physical_protect_now(int all)
 		offset = 0;
 		size = CONFIG_FLASH_PHYSICAL_SIZE;
 	} else {
-		offset = CONFIG_FW_RO_OFF;
-		size = CONFIG_FW_RO_SIZE;
+		offset = CONFIG_RO_MEM_OFF;
+		size = CONFIG_RO_SIZE;
 	}
 
 	spi_enable(1);
@@ -145,10 +145,10 @@ uint32_t flash_physical_get_protect_flags(void)
 	uint32_t flags = 0;
 
 	spi_enable(1);
-	if (spi_flash_check_protect(CONFIG_FW_RO_OFF, CONFIG_FW_RO_SIZE)) {
+	if (spi_flash_check_protect(CONFIG_RO_MEM_OFF, CONFIG_RO_SIZE)) {
 		flags |= EC_FLASH_PROTECT_RO_AT_BOOT | EC_FLASH_PROTECT_RO_NOW;
-		if (spi_flash_check_protect(CONFIG_FW_RW_OFF,
-					    CONFIG_FW_RW_SIZE))
+		if (spi_flash_check_protect(CONFIG_RW_MEM_OFF,
+					    CONFIG_RW_SIZE))
 			flags |= EC_FLASH_PROTECT_ALL_NOW;
 	}
 	spi_enable(0);
@@ -206,8 +206,8 @@ int flash_physical_protect_at_boot(enum flash_wp_range range)
 		offset = size = 0;
 		break;
 	case FLASH_WP_RO:
-		offset = CONFIG_FW_RO_OFF;
-		size = CONFIG_FW_RO_SIZE;
+		offset = CONFIG_RO_MEM_OFF;
+		size = CONFIG_RO_SIZE;
 		break;
 	case FLASH_WP_ALL:
 		offset = 0;
diff --git a/chip/mec1322/lfw/ec_lfw.c b/chip/mec1322/lfw/ec_lfw.c
index 0d953e6ae9..2ceaa35644 100644
--- a/chip/mec1322/lfw/ec_lfw.c
+++ b/chip/mec1322/lfw/ec_lfw.c
@@ -87,14 +87,14 @@ static int spi_flash_readloc(uint8_t *buf_usr,
 
 int spi_rwimage_load(void)
 {
-	uint8_t *buf = (uint8_t *) (CONFIG_FW_RW_OFF + CONFIG_FLASH_BASE);
+	uint8_t *buf = (uint8_t *) (CONFIG_RW_MEM_OFF + CONFIG_FLASH_BASE);
 	uint32_t i;
 
-	memset((void *)buf, 0xFF, (CONFIG_FW_RW_SIZE - 4));
+	memset((void *)buf, 0xFF, (CONFIG_RW_SIZE - 4));
 
 	spi_enable(1);
 
-	for (i = 0; i < CONFIG_FW_RW_SIZE; i += SPI_CHUNK_SIZE)
+	for (i = 0; i < CONFIG_RW_SIZE; i += SPI_CHUNK_SIZE)
 		spi_flash_readloc(&buf[i],
 					CONFIG_RW_IMAGE_FLASHADDR + i,
 					SPI_CHUNK_SIZE);
@@ -226,11 +226,11 @@ void lfw_main()
 
 	switch (*image_type) {
 	case SYSTEM_IMAGE_RW:
-		init_addr = CONFIG_FW_RW_OFF + CONFIG_FLASH_BASE;
+		init_addr = CONFIG_RW_MEM_OFF + CONFIG_FLASH_BASE;
 		spi_rwimage_load();
 	case SYSTEM_IMAGE_RO:
 	default:
-		init_addr = CONFIG_FW_RO_OFF + CONFIG_FLASH_BASE;
+		init_addr = CONFIG_RO_MEM_OFF + CONFIG_FLASH_BASE;
 	}
 
 	jump_to_image(*(uintptr_t *)(init_addr + 4));
diff --git a/chip/mec1322/system.c b/chip/mec1322/system.c
index b94e93ff07..2460dc51b2 100644
--- a/chip/mec1322/system.c
+++ b/chip/mec1322/system.c
@@ -379,5 +379,5 @@ enum system_image_copy_t system_get_shrspi_image_copy(void)
 /* TODO(crosbug.com/p/37510): Implement bootloader */
 uint32_t system_get_lfw_address(uint32_t flash_addr)
 {
-	return CONFIG_FW_RO_OFF;
+	return CONFIG_RO_MEM_OFF;
 }
diff --git a/chip/npcx/config_chip.h b/chip/npcx/config_chip.h
index b6fc1d1f3a..560be8e6c9 100644
--- a/chip/npcx/config_chip.h
+++ b/chip/npcx/config_chip.h
@@ -75,17 +75,17 @@
 #endif
 
 /* RO firmware offset of flash */
-#define CONFIG_FW_RO_OFF	0
-#define CONFIG_FW_RO_SIZE       CONFIG_FW_IMAGE_SIZE
+#define CONFIG_RO_MEM_OFF       0
+#define CONFIG_RO_SIZE          CONFIG_FW_IMAGE_SIZE
 #define CONFIG_FLASH_SIZE       CONFIG_FLASH_PHYSICAL_SIZE
 
 /* RW firmware is one firmware image offset from the start */
-#define CONFIG_FW_RW_OFF        CONFIG_FW_IMAGE_SIZE
-#define CONFIG_FW_RW_SIZE       CONFIG_FW_IMAGE_SIZE
+#define CONFIG_RW_MEM_OFF       CONFIG_FW_IMAGE_SIZE
+#define CONFIG_RW_SIZE          CONFIG_FW_IMAGE_SIZE
 
 /* TODO(crosbug.com/p/23796): why 2 sets of configs with the same numbers? */
-#define CONFIG_FW_WP_RO_OFF     CONFIG_FW_RO_OFF
-#define CONFIG_FW_WP_RO_SIZE    CONFIG_FW_RO_SIZE
+#define CONFIG_WP_OFF           CONFIG_RO_MEM_OFF
+#define CONFIG_WP_SIZE          CONFIG_RO_SIZE
 
 /*
  * The offset from top of flash wich used by booter
diff --git a/chip/npcx/lfw/ec_lfw.c b/chip/npcx/lfw/ec_lfw.c
index e9710398f3..c3a505ce69 100644
--- a/chip/npcx/lfw/ec_lfw.c
+++ b/chip/npcx/lfw/ec_lfw.c
@@ -83,12 +83,12 @@ bin2ram(void)
 {
 	/* copy image from RO base */
 	if (IS_BIT_SET(NPCX_FWCTRL, NPCX_FWCTRL_RO_REGION))
-		flash_burst_copy_fw_to_mram(CONFIG_FW_RO_OFF, CONFIG_CDRAM_BASE,
-				CONFIG_FW_RO_SIZE - LFW_SIZE);
+		flash_burst_copy_fw_to_mram(CONFIG_RO_MEM_OFF,
+			CONFIG_CDRAM_BASE, CONFIG_RO_SIZE - LFW_SIZE);
 	/* copy image from RW base */
 	else
-		flash_burst_copy_fw_to_mram(CONFIG_FW_RW_OFF, CONFIG_CDRAM_BASE,
-				CONFIG_FW_RW_SIZE - LFW_SIZE);
+		flash_burst_copy_fw_to_mram(CONFIG_RW_MEM_OFF,
+			CONFIG_CDRAM_BASE, CONFIG_RW_SIZE - LFW_SIZE);
 
 	/* Disable FIU pins to tri-state */
 	CLEAR_BIT(NPCX_DEVCNT, NPCX_DEVCNT_F_SPI_TRIS);
diff --git a/chip/npcx/system.c b/chip/npcx/system.c
index 44f5c03f64..a103292e0e 100644
--- a/chip/npcx/system.c
+++ b/chip/npcx/system.c
@@ -854,7 +854,7 @@ enum system_image_copy_t system_get_shrspi_image_copy(void)
 static void system_sysjump(void)
 {
 	/* Jump to RO region -- set flag */
-	if (base_addr == CONFIG_FLASH_BASE + CONFIG_FW_RO_OFF)
+	if (base_addr == CONFIG_FLASH_BASE + CONFIG_RO_MEM_OFF)
 		SET_BIT(NPCX_FWCTRL, NPCX_FWCTRL_RO_REGION);
 	else /* Jump to RW region -- clear flag */
 		CLEAR_BIT(NPCX_FWCTRL, NPCX_FWCTRL_RO_REGION);
diff --git a/chip/nrf51/config_chip.h b/chip/nrf51/config_chip.h
index 9de7b1eb76..104fceb0ca 100644
--- a/chip/nrf51/config_chip.h
+++ b/chip/nrf51/config_chip.h
@@ -48,17 +48,17 @@
 #define CONFIG_FW_IMAGE_SIZE    (128 * 1024)
 
 /* Define the RO/RW offset */
-#define CONFIG_FW_RO_OFF        0
-#define CONFIG_FW_RO_SIZE       (CONFIG_FW_IMAGE_SIZE - CONFIG_FW_PSTATE_SIZE)
-#define CONFIG_FW_RW_OFF        CONFIG_FW_IMAGE_SIZE
-#define CONFIG_FW_RW_SIZE       CONFIG_FW_IMAGE_SIZE
+#define CONFIG_RO_MEM_OFF       0
+#define CONFIG_RO_SIZE          (CONFIG_FW_IMAGE_SIZE - CONFIG_FW_PSTATE_SIZE)
+#define CONFIG_RW_MEM_OFF       CONFIG_FW_IMAGE_SIZE
+#define CONFIG_RW_SIZE          CONFIG_FW_IMAGE_SIZE
 
 /*
  * Put pstate after RO to give RW more space and make RO write protect
  * region contiguous.
  */
-#define CONFIG_FW_PSTATE_SIZE  CONFIG_FLASH_BANK_SIZE
-#define CONFIG_FW_PSTATE_OFF   (CONFIG_FW_RO_OFF + CONFIG_FW_RO_SIZE)
+#define CONFIG_FW_PSTATE_SIZE   CONFIG_FLASH_BANK_SIZE
+#define CONFIG_FW_PSTATE_OFF    (CONFIG_RO_MEM_OFF + CONFIG_RO_SIZE)
 
 
 /* Number of IRQ vectors on the NVIC */
diff --git a/chip/stm32/config-stm32f03x.h b/chip/stm32/config-stm32f03x.h
index a1211d38a7..2bd4da74cb 100644
--- a/chip/stm32/config-stm32f03x.h
+++ b/chip/stm32/config-stm32f03x.h
@@ -20,12 +20,12 @@
 /* Size of one firmware image in flash */
 #define CONFIG_FW_IMAGE_SIZE    (16 * 1024)
 
-#define CONFIG_FW_RO_OFF        0
-#define CONFIG_FW_RO_SIZE       (CONFIG_FW_IMAGE_SIZE - CONFIG_FW_PSTATE_SIZE)
-#define CONFIG_FW_RW_OFF        CONFIG_FW_IMAGE_SIZE
-#define CONFIG_FW_RW_SIZE       CONFIG_FW_IMAGE_SIZE
-#define CONFIG_FW_WP_RO_OFF     CONFIG_FW_RO_OFF
-#define CONFIG_FW_WP_RO_SIZE    CONFIG_FW_IMAGE_SIZE
+#define CONFIG_RO_MEM_OFF       0
+#define CONFIG_RO_SIZE          (CONFIG_FW_IMAGE_SIZE - CONFIG_FW_PSTATE_SIZE)
+#define CONFIG_RW_MEM_OFF       CONFIG_FW_IMAGE_SIZE
+#define CONFIG_RW_SIZE          CONFIG_FW_IMAGE_SIZE
+#define CONFIG_WP_OFF           CONFIG_RO_MEM_OFF
+#define CONFIG_WP_SIZE          CONFIG_FW_IMAGE_SIZE
 
 /*
  * Put pstate after RO to give RW more space and make RO write protect region
@@ -37,7 +37,7 @@
 #else
 #define CONFIG_FW_PSTATE_SIZE   CONFIG_FLASH_BANK_SIZE
 #endif
-#define CONFIG_FW_PSTATE_OFF    (CONFIG_FW_RO_OFF + CONFIG_FW_RO_SIZE)
+#define CONFIG_FW_PSTATE_OFF    (CONFIG_RO_MEM_OFF + CONFIG_RO_SIZE)
 
 /* Number of IRQ vectors on the NVIC */
 #define CONFIG_IRQ_COUNT 32
diff --git a/chip/stm32/config-stm32f07x.h b/chip/stm32/config-stm32f07x.h
index 1b652cfb66..d1d01824e9 100644
--- a/chip/stm32/config-stm32f07x.h
+++ b/chip/stm32/config-stm32f07x.h
@@ -20,19 +20,19 @@
 /* Size of the first firmware image in flash */
 #define CONFIG_FW_IMAGE_SIZE    (CONFIG_FLASH_SIZE / 2)
 
-#define CONFIG_FW_RO_OFF        0
-#define CONFIG_FW_RO_SIZE       (CONFIG_FW_IMAGE_SIZE - CONFIG_FW_PSTATE_SIZE)
-#define CONFIG_FW_RW_OFF        (CONFIG_FW_RO_OFF + CONFIG_FW_IMAGE_SIZE)
-#define CONFIG_FW_RW_SIZE       (CONFIG_FLASH_SIZE - CONFIG_FW_IMAGE_SIZE)
-#define CONFIG_FW_WP_RO_OFF     CONFIG_FW_RO_OFF
-#define CONFIG_FW_WP_RO_SIZE    CONFIG_FW_IMAGE_SIZE
+#define CONFIG_RO_MEM_OFF       0
+#define CONFIG_RO_SIZE          (CONFIG_FW_IMAGE_SIZE - CONFIG_FW_PSTATE_SIZE)
+#define CONFIG_RW_MEM_OFF       (CONFIG_RO_MEM_OFF + CONFIG_FW_IMAGE_SIZE)
+#define CONFIG_RW_SIZE          (CONFIG_FLASH_SIZE - CONFIG_FW_IMAGE_SIZE)
+#define CONFIG_WP_OFF           CONFIG_RO_MEM_OFF
+#define CONFIG_WP_SIZE          CONFIG_FW_IMAGE_SIZE
 
 /*
  * Put pstate after RO to give RW more space and make RO write protect region
  * contiguous.
  */
 #define CONFIG_FW_PSTATE_SIZE   CONFIG_FLASH_BANK_SIZE
-#define CONFIG_FW_PSTATE_OFF    (CONFIG_FW_RO_OFF + CONFIG_FW_RO_SIZE)
+#define CONFIG_FW_PSTATE_OFF    (CONFIG_RO_MEM_OFF + CONFIG_RO_SIZE)
 
 /* Number of IRQ vectors on the NVIC */
 #define CONFIG_IRQ_COUNT 32
diff --git a/chip/stm32/config-stm32f100.h b/chip/stm32/config-stm32f100.h
index 92b5ab4dca..297da6b238 100644
--- a/chip/stm32/config-stm32f100.h
+++ b/chip/stm32/config-stm32f100.h
@@ -20,19 +20,19 @@
 /* Size of one firmware image in flash */
 #define CONFIG_FW_IMAGE_SIZE    (64 * 1024)
 
-#define CONFIG_FW_RO_OFF        0
-#define CONFIG_FW_RO_SIZE       (CONFIG_FW_IMAGE_SIZE - CONFIG_FW_PSTATE_SIZE)
-#define CONFIG_FW_RW_OFF        CONFIG_FW_IMAGE_SIZE
-#define CONFIG_FW_RW_SIZE       CONFIG_FW_IMAGE_SIZE
-#define CONFIG_FW_WP_RO_OFF     CONFIG_FW_RO_OFF
-#define CONFIG_FW_WP_RO_SIZE    CONFIG_FW_IMAGE_SIZE
+#define CONFIG_RO_MEM_OFF       0
+#define CONFIG_RO_SIZE          (CONFIG_FW_IMAGE_SIZE - CONFIG_FW_PSTATE_SIZE)
+#define CONFIG_RW_MEM_OFF       CONFIG_FW_IMAGE_SIZE
+#define CONFIG_RW_SIZE          CONFIG_FW_IMAGE_SIZE
+#define CONFIG_WP_OFF           CONFIG_RO_MEM_OFF
+#define CONFIG_WP_SIZE          CONFIG_FW_IMAGE_SIZE
 
 /*
  * Put pstate after RO to give RW more space and make RO write protect region
  * contiguous.
  */
 #define CONFIG_FW_PSTATE_SIZE   CONFIG_FLASH_BANK_SIZE
-#define CONFIG_FW_PSTATE_OFF    (CONFIG_FW_RO_OFF + CONFIG_FW_RO_SIZE)
+#define CONFIG_FW_PSTATE_OFF    (CONFIG_RO_MEM_OFF + CONFIG_RO_SIZE)
 
 /* Number of IRQ vectors on the NVIC */
 #define CONFIG_IRQ_COUNT 61
diff --git a/chip/stm32/config-stm32f10x.h b/chip/stm32/config-stm32f10x.h
index a201f52c4f..e638fdd377 100644
--- a/chip/stm32/config-stm32f10x.h
+++ b/chip/stm32/config-stm32f10x.h
@@ -20,19 +20,19 @@
 /* Size of one firmware image in flash */
 #define CONFIG_FW_IMAGE_SIZE    (64 * 1024)
 
-#define CONFIG_FW_RO_OFF        0
-#define CONFIG_FW_RO_SIZE       (CONFIG_FW_IMAGE_SIZE - CONFIG_FW_PSTATE_SIZE)
-#define CONFIG_FW_RW_OFF        CONFIG_FW_IMAGE_SIZE
-#define CONFIG_FW_RW_SIZE       CONFIG_FW_IMAGE_SIZE
-#define CONFIG_FW_WP_RO_OFF     CONFIG_FW_RO_OFF
-#define CONFIG_FW_WP_RO_SIZE    CONFIG_FW_IMAGE_SIZE
+#define CONFIG_RO_MEM_OFF       0
+#define CONFIG_RO_SIZE          (CONFIG_FW_IMAGE_SIZE - CONFIG_FW_PSTATE_SIZE)
+#define CONFIG_RW_MEM_OFF       CONFIG_FW_IMAGE_SIZE
+#define CONFIG_RW_SIZE          CONFIG_FW_IMAGE_SIZE
+#define CONFIG_WP_OFF           CONFIG_RO_MEM_OFF
+#define CONFIG_WP_SIZE          CONFIG_FW_IMAGE_SIZE
 
 /*
  * Put pstate after RO to give RW more space and make RO write protect region
  * contiguous.
  */
 #define CONFIG_FW_PSTATE_SIZE   CONFIG_FLASH_BANK_SIZE
-#define CONFIG_FW_PSTATE_OFF    (CONFIG_FW_RO_OFF + CONFIG_FW_RO_SIZE)
+#define CONFIG_FW_PSTATE_OFF    (CONFIG_RO_MEM_OFF + CONFIG_RO_SIZE)
 
 /* Number of IRQ vectors on the NVIC */
 #define CONFIG_IRQ_COUNT 68
diff --git a/chip/stm32/config-stm32f373.h b/chip/stm32/config-stm32f373.h
index 32a9d0b5fa..05f50f9cdd 100644
--- a/chip/stm32/config-stm32f373.h
+++ b/chip/stm32/config-stm32f373.h
@@ -20,19 +20,19 @@
 /* Size of one firmware image in flash */
 #define CONFIG_FW_IMAGE_SIZE    (128 * 1024)
 
-#define CONFIG_FW_RO_OFF        0
-#define CONFIG_FW_RO_SIZE       (CONFIG_FW_IMAGE_SIZE - CONFIG_FW_PSTATE_SIZE)
-#define CONFIG_FW_RW_OFF        CONFIG_FW_IMAGE_SIZE
-#define CONFIG_FW_RW_SIZE       CONFIG_FW_IMAGE_SIZE
-#define CONFIG_FW_WP_RO_OFF     CONFIG_FW_RO_OFF
-#define CONFIG_FW_WP_RO_SIZE    CONFIG_FW_IMAGE_SIZE
+#define CONFIG_RO_MEM_OFF       0
+#define CONFIG_RO_SIZE          (CONFIG_FW_IMAGE_SIZE - CONFIG_FW_PSTATE_SIZE)
+#define CONFIG_RW_MEM_OFF       CONFIG_FW_IMAGE_SIZE
+#define CONFIG_RW_SIZE          CONFIG_FW_IMAGE_SIZE
+#define CONFIG_WP_OFF           CONFIG_RO_MEM_OFF
+#define CONFIG_WP_SIZE          CONFIG_FW_IMAGE_SIZE
 
 /*
  * Put pstate after RO to give RW more space and make RO write protect region
  * contiguous.
  */
 #define CONFIG_FW_PSTATE_SIZE   CONFIG_FLASH_BANK_SIZE
-#define CONFIG_FW_PSTATE_OFF    (CONFIG_FW_RO_OFF + CONFIG_FW_RO_SIZE)
+#define CONFIG_FW_PSTATE_OFF    (CONFIG_RO_MEM_OFF + CONFIG_RO_SIZE)
 
 /* Number of IRQ vectors on the NVIC */
 #define CONFIG_IRQ_COUNT 81
diff --git a/chip/stm32/config-stm32l100.h b/chip/stm32/config-stm32l100.h
index 983f956b84..ae063be847 100644
--- a/chip/stm32/config-stm32l100.h
+++ b/chip/stm32/config-stm32l100.h
@@ -29,19 +29,19 @@
 /* Size of one firmware image in flash */
 #define CONFIG_FW_IMAGE_SIZE    (64 * 1024)
 
-#define CONFIG_FW_RO_OFF        0
-#define CONFIG_FW_RO_SIZE       (CONFIG_FW_IMAGE_SIZE - CONFIG_FW_PSTATE_SIZE)
-#define CONFIG_FW_RW_OFF        CONFIG_FW_IMAGE_SIZE
-#define CONFIG_FW_RW_SIZE       CONFIG_FW_IMAGE_SIZE
-#define CONFIG_FW_WP_RO_OFF     CONFIG_FW_RO_OFF
-#define CONFIG_FW_WP_RO_SIZE    CONFIG_FW_RO_SIZE
+#define CONFIG_RO_MEM_OFF       0
+#define CONFIG_RO_SIZE          (CONFIG_FW_IMAGE_SIZE - CONFIG_FW_PSTATE_SIZE)
+#define CONFIG_RW_MEM_OFF       CONFIG_FW_IMAGE_SIZE
+#define CONFIG_RW_SIZE          CONFIG_FW_IMAGE_SIZE
+#define CONFIG_WP_OFF           CONFIG_RO_MEM_OFF
+#define CONFIG_WP_SIZE          CONFIG_RO_SIZE
 
 /*
  * Put pstate after RO to give RW more space and make RO write protect
  * region contiguous.
  */
 #define CONFIG_FW_PSTATE_SIZE  CONFIG_FLASH_BANK_SIZE
-#define CONFIG_FW_PSTATE_OFF   (CONFIG_FW_RO_OFF + CONFIG_FW_RO_SIZE)
+#define CONFIG_FW_PSTATE_OFF   (CONFIG_RO_MEM_OFF + CONFIG_RO_SIZE)
 
 /* Number of IRQ vectors on the NVIC */
 #define CONFIG_IRQ_COUNT 45
diff --git a/chip/stm32/config-stm32l15x.h b/chip/stm32/config-stm32l15x.h
index 4ba9fe24b5..4e5a9dca06 100644
--- a/chip/stm32/config-stm32l15x.h
+++ b/chip/stm32/config-stm32l15x.h
@@ -29,19 +29,19 @@
 /* Size of one firmware image in flash */
 #define CONFIG_FW_IMAGE_SIZE    (64 * 1024)
 
-#define CONFIG_FW_RO_OFF        0
-#define CONFIG_FW_RO_SIZE       (CONFIG_FW_IMAGE_SIZE - CONFIG_FW_PSTATE_SIZE)
-#define CONFIG_FW_RW_OFF        CONFIG_FW_IMAGE_SIZE
-#define CONFIG_FW_RW_SIZE       CONFIG_FW_IMAGE_SIZE
-#define CONFIG_FW_WP_RO_OFF     CONFIG_FW_RO_OFF
-#define CONFIG_FW_WP_RO_SIZE    CONFIG_FW_RO_SIZE
+#define CONFIG_RO_MEM_OFF       0
+#define CONFIG_RO_SIZE          (CONFIG_FW_IMAGE_SIZE - CONFIG_FW_PSTATE_SIZE)
+#define CONFIG_RW_MEM_OFF       CONFIG_FW_IMAGE_SIZE
+#define CONFIG_RW_SIZE          CONFIG_FW_IMAGE_SIZE
+#define CONFIG_WP_OFF           CONFIG_RO_MEM_OFF
+#define CONFIG_WP_SIZE          CONFIG_RO_SIZE
 
 /*
  * Put pstate after RO to give RW more space and make RO write protect
  * region contiguous.
  */
-#define CONFIG_FW_PSTATE_SIZE  CONFIG_FLASH_BANK_SIZE
-#define CONFIG_FW_PSTATE_OFF   (CONFIG_FW_RO_OFF + CONFIG_FW_RO_SIZE)
+#define CONFIG_FW_PSTATE_SIZE   CONFIG_FLASH_BANK_SIZE
+#define CONFIG_FW_PSTATE_OFF    (CONFIG_RO_MEM_OFF + CONFIG_RO_SIZE)
 
 /* Number of IRQ vectors on the NVIC */
 #define CONFIG_IRQ_COUNT 45
diff --git a/chip/stm32/config-stm32ts60.h b/chip/stm32/config-stm32ts60.h
index 0713b201d6..85a78af6d5 100644
--- a/chip/stm32/config-stm32ts60.h
+++ b/chip/stm32/config-stm32ts60.h
@@ -20,19 +20,19 @@
 /* Size of one firmware image in flash */
 #define CONFIG_FW_IMAGE_SIZE    (32 * 1024)
 
-#define CONFIG_FW_RO_OFF        0
-#define CONFIG_FW_RO_SIZE       (CONFIG_FW_IMAGE_SIZE - CONFIG_FW_PSTATE_SIZE)
-#define CONFIG_FW_RW_OFF        CONFIG_FW_IMAGE_SIZE
-#define CONFIG_FW_RW_SIZE       CONFIG_FW_IMAGE_SIZE
-#define CONFIG_FW_WP_RO_OFF     CONFIG_FW_RO_OFF
-#define CONFIG_FW_WP_RO_SIZE    CONFIG_FW_IMAGE_SIZE
+#define CONFIG_RO_MEM_OFF       0
+#define CONFIG_RO_SIZE          (CONFIG_FW_IMAGE_SIZE - CONFIG_FW_PSTATE_SIZE)
+#define CONFIG_RW_MEM_OFF       CONFIG_FW_IMAGE_SIZE
+#define CONFIG_RW_SIZE          CONFIG_FW_IMAGE_SIZE
+#define CONFIG_WP_OFF           CONFIG_RO_MEM_OFF
+#define CONFIG_WP_SIZE          CONFIG_FW_IMAGE_SIZE
 
 /*
  * Put pstate after RO to give RW more space and make RO write protect region
  * contiguous.
  */
 #define CONFIG_FW_PSTATE_SIZE   CONFIG_FLASH_BANK_SIZE
-#define CONFIG_FW_PSTATE_OFF    (CONFIG_FW_RO_OFF + CONFIG_FW_RO_SIZE)
+#define CONFIG_FW_PSTATE_OFF    (CONFIG_RO_MEM_OFF + CONFIG_RO_SIZE)
 
 /* Number of IRQ vectors on the NVIC */
 #define CONFIG_IRQ_COUNT 59