diff options
| author | Randall Spangler <rspangler@chromium.org> | 2013-10-25 10:26:16 -0700 |
|---|---|---|
| committer | chrome-internal-fetch <chrome-internal-fetch@google.com> | 2013-10-31 18:43:39 +0000 |
| commit | 2dc1418ccdad1b06f686cddc717e02bcb80ff648 (patch) | |
| tree | 3feb80ddd776a1c641fbc37b111cf3a06edceb3d /chip | |
| parent | d16a246ea9c7d5982d4eb932c09310146ab3463e (diff) | |
| download | chrome-ec-2dc1418ccdad1b06f686cddc717e02bcb80ff648.tar.gz | |
cleanup: Assorted TODO comments
Remove comments if no longer applicable, or assign bug numbers if they
still are. Tidy some debug output. No code changes other than the
debug output.
BUG=chrome-os-partner:18343
BRANCH=none
TEST=build all platforms, pass unit tests
Change-Id: I2277e73fbf8cc93f3b1b35ee115e0f2f52eb8cf9
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/175215
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Diffstat (limited to 'chip')
| -rw-r--r-- | chip/lm4/gpio.c | 3 | ||||
| -rw-r--r-- | chip/lm4/peci.c | 17 |
2 files changed, 15 insertions, 5 deletions
diff --git a/chip/lm4/gpio.c b/chip/lm4/gpio.c index 38b5e7ed46..7bed71bbc6 100644 --- a/chip/lm4/gpio.c +++ b/chip/lm4/gpio.c @@ -47,8 +47,9 @@ void gpio_set_alternate_function(uint32_t port, uint32_t mask, int func) int port_index = find_gpio_port_index(port); int cgmask; + /* Ignore (do nothing for) invalid port values */ if (port_index < 0) - return; /* TODO: assert */ + return; /* Enable the GPIO port in run and sleep. */ cgmask = 1 << port_index; diff --git a/chip/lm4/peci.c b/chip/lm4/peci.c index 7f0d692439..74f081d6c4 100644 --- a/chip/lm4/peci.c +++ b/chip/lm4/peci.c @@ -16,8 +16,13 @@ #include "temp_sensor.h" #include "util.h" -/* Max junction temperature for processor in degrees C */ -/* TODO: read TjMax from processor via PECI */ +/* + * Max junction temperature for processor in degrees C. This is correct for + * Ivy Bridge and Haswell; future chips don't have PECI. + * + * In theory we could read TjMax from the processor via PECI, but that requires + * closed-source Intel PECI commands. + */ #define PECI_TJMAX 105 /* Initial PECI baud rate */ @@ -26,8 +31,12 @@ /* Polling interval for PECI, in ms */ #define PECI_POLL_INTERVAL_MS 250 -/* Internal and external path delays, in ns */ -#define PECI_TD_FET_NS 60 /* Guess; TODO: what is real delay */ +/* + * Internal and external path delays, in ns. The external delay is a + * best-guess measurement, but we're fairly tolerant of a bad guess because + * PECI_BAUD_RATE is slow compared to PECI's actual maximum baud rate. + */ +#define PECI_TD_FET_NS 60 #define PECI_TD_INT_NS 80 /* Number of controller retries. Should be between 0 and 7. */ |