Use SECOND and MSEC constants

We'd defined them in a number of different files.  This moves
definitions to timer.h, and uses them everywhere we have large delays
(since 10*SECOND is less typo-prone than 10000000).

Also add msleep() and sleep() inline functions.  No need for mdelay()
or delay(), since any delays that long should use sleep funcs instead
of spin-waiting.

BUG=chrome-os-partner:15579
BRANCH=none
TEST=boot system; taskinfo displays similar numbers to before

Change-Id: I2a92a9f10f46b6b7b6571759b1f8ab4ecfbf8259
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/36726

16 files changed, 73 insertions, 85 deletions

diff --git a/chip/lm4/adc.c b/chip/lm4/adc.c
index 254b0903af..b2d3479eef 100644
--- a/chip/lm4/adc.c
+++ b/chip/lm4/adc.c
@@ -96,7 +96,7 @@ int lm4_adc_flush_and_read(enum lm4_adc_sequencer seq)
 	LM4_ADC_ADCPSSI |= 0x01 << seq;
 
 	/* Wait for interrupt */
-	event = task_wait_event(1000000);
+	event = task_wait_event(SECOND);
 	task_waiting_on_ss[seq] = TASK_ID_INVALID;
 	if (event == TASK_EVENT_TIMER)
 		return ADC_READ_ERROR;
diff --git a/chip/lm4/eeprom.c b/chip/lm4/eeprom.c
index ff414ede24..7b28712afd 100644
--- a/chip/lm4/eeprom.c
+++ b/chip/lm4/eeprom.c
@@ -19,7 +19,6 @@
 /* Count of EEPROM blocks */
 static int block_count;
 
-
 /*
  * Wait for the current EEPROM operation to finish; all operations but write
  * should normally finish in 4 system clocks, but worst case is up to
@@ -32,7 +31,7 @@ static int wait_for_done(void)
 	int j;
 
 	for (j = 0; j < 20; j++) {  /* 20 * 100 ms = 2000 ms */
-		uint64_t tstop = get_time().val + 100000;  /* 100ms from now */
+		uint64_t tstop = get_time().val + 100 * MSEC;
 		while (get_time().val < tstop) {
 			if (!(LM4_EEPROM_EEDONE & 0x01))
 				return EC_SUCCESS;
diff --git a/chip/lm4/flash.c b/chip/lm4/flash.c
index 8a9c3dc946..e06246b7ee 100644
--- a/chip/lm4/flash.c
+++ b/chip/lm4/flash.c
@@ -243,7 +243,7 @@ int flash_physical_erase(int offset, int size)
 #ifdef CONFIG_TASK_WATCHDOG
 		/* Reload the watchdog timer, so that erasing many flash pages
 		 * doesn't cause a watchdog reset.  May not need this now that
-		 * we're using usleep() below. */
+		 * we're using msleep() below. */
 		watchdog_reload();
 #endif
 
@@ -254,7 +254,7 @@ int flash_physical_erase(int offset, int size)
 		for (t = 0; LM4_FLASH_FMC & 0x02; t++) {
 			if (t > ERASE_TIMEOUT_MS)
 				return EC_ERROR_TIMEOUT;
-			usleep(1000);
+			msleep(1);
 		}
 
 		/* Check for error conditions - erase failed, voltage error,
diff --git a/chip/lm4/hwtimer.c b/chip/lm4/hwtimer.c
index 45166f2194..cbf28f5294 100644
--- a/chip/lm4/hwtimer.c
+++ b/chip/lm4/hwtimer.c
@@ -5,14 +5,13 @@
 
 /* Hardware timers driver */
 
-#include "board.h"
 #include "clock.h"
+#include "common.h"
 #include "hooks.h"
 #include "hwtimer.h"
 #include "registers.h"
 #include "task.h"
-
-#define US_PER_SECOND 1000000
+#include "timer.h"
 
 void __hw_clock_event_set(uint32_t deadline)
 {
@@ -22,63 +21,60 @@ void __hw_clock_event_set(uint32_t deadline)
 	LM4_TIMER_IMR(6) |= 0x10;
 }
 
-
 uint32_t __hw_clock_event_get(void)
 {
 	return 0xffffffff - LM4_TIMER_TAMATCHR(6);
 }
 
-
 void __hw_clock_event_clear(void)
 {
 	/* Disable the match interrupt */
 	LM4_TIMER_IMR(6) &= ~0x10;
 }
 
-
 uint32_t __hw_clock_source_read(void)
 {
 	return 0xffffffff - LM4_TIMER_TAV(6);
 }
 
-
 void __hw_clock_source_set(uint32_t ts)
 {
 	LM4_TIMER_TAV(6) = 0xffffffff - ts;
 }
 
-
 static void __hw_clock_source_irq(void)
 {
 	uint32_t status = LM4_TIMER_RIS(6);
 
-	/* clear interrupt */
+	/* Clear interrupt */
 	LM4_TIMER_ICR(6) = status;
 
 	/*
-	 * Find expired timers and set the new timer deadline
-	 * get from the IRQ status if the free running counter as overflowed
+	 * Find expired timers and set the new timer deadline; check the IRQ
+	 * status to determine if the free-running counter overflowed.
 	 */
 	process_timers(status & 0x01);
 }
 DECLARE_IRQ(LM4_IRQ_TIMERW0A, __hw_clock_source_irq, 1);
 
-
 static void update_prescaler(void)
 {
-	/* Set the prescaler to increment every microsecond.  This takes
-	 * effect immediately, because the TAILD bit in TAMR is clear. */
-	LM4_TIMER_TAPR(6) = clock_get_freq() / US_PER_SECOND;
+	/*
+	 * Set the prescaler to increment every microsecond.  This takes
+	 * effect immediately, because the TAILD bit in TAMR is clear.
+	 */
+	LM4_TIMER_TAPR(6) = clock_get_freq() / SECOND;
 }
 DECLARE_HOOK(HOOK_FREQ_CHANGE, update_prescaler, HOOK_PRIO_DEFAULT);
 
-
 int __hw_clock_source_init(uint32_t start_t)
 {
 	volatile uint32_t scratch __attribute__((unused));
 
-	/* Use WTIMER0 (timer 6) configured as a free running counter with 1 us
-	 * period */
+	/*
+	 * Use WTIMER0 (timer 6) configured as a free running counter with 1 us
+	 * period.
+	 */
 
 	/* Enable WTIMER0 clock */
 	LM4_SYSTEM_RCGCWTIMER |= 1;
@@ -101,8 +97,11 @@ int __hw_clock_source_init(uint32_t start_t)
 	LM4_TIMER_TAILR(6) = 0xffffffff;
 	/* Starts counting in timer A */
 	LM4_TIMER_CTL(6) |= 0x1;
-	/* Override the count with the start value now that counting has
-	 * started. */
+
+	/*
+	 * Override the count with the start value now that counting has
+	 * started.
+	 */
 	__hw_clock_source_set(start_t);
 
 	/* Enable interrupt */
diff --git a/chip/lm4/i2c.c b/chip/lm4/i2c.c
index 0fdefc15d9..7f0fa19c95 100644
--- a/chip/lm4/i2c.c
+++ b/chip/lm4/i2c.c
@@ -61,7 +61,7 @@ static int wait_idle(int port)
 		 * the I2C is either completed or timed out. Refer to the
 		 * implementation of usleep() for a similar situation.
 		 */
-		event |= (task_wait_event(1000000) & ~TASK_EVENT_I2C_IDLE);
+		event |= (task_wait_event(SECOND) & ~TASK_EVENT_I2C_IDLE);
 		LM4_I2C_MIMR(port) = 0x00;
 		task_waiting_on_port[port] = TASK_ID_INVALID;
 		if (event & TASK_EVENT_TIMER) {
diff --git a/chip/lm4/keyboard_scan.c b/chip/lm4/keyboard_scan.c
index a07170dcfe..1d25b1937b 100644
--- a/chip/lm4/keyboard_scan.c
+++ b/chip/lm4/keyboard_scan.c
@@ -24,15 +24,15 @@
 #define CPRINTF(format, args...) cprintf(CC_KEYSCAN, format, ## args)
 
 /* Time constants */
-#define POLLING_MODE_TIMEOUT 1000000  /* Max time to poll if no keys are down */
-#define DEBOUNCE_UP_US         30000  /* Debounce time for key-up */
-#define DEBOUNCE_DOWN_US        6000  /* Debounce time for key-down */
-#define SCAN_LOOP_DELAY         1000  /* Delay in scan loop */
+#define POLLING_MODE_TIMEOUT  SECOND  /* Max time to poll if no keys are down */
+#define DEBOUNCE_UP_US   (30 * MSEC)  /* Debounce time for key-up */
+#define DEBOUNCE_DOWN_US  (6 * MSEC)  /* Debounce time for key-down */
+#define SCAN_LOOP_DELAY         MSEC  /* Delay in scan loop */
 #define COLUMN_CHARGE_US          40  /* Column charge time in usec */
 
 #define KB_COLS 13
 
-#define SCAN_TIME_COUNT 32
+#define SCAN_TIME_COUNT 32  /* Number of last scan times to track */
 
 /* Boot key list.  Must be in same order as enum boot_key. */
 struct boot_key_entry {
diff --git a/chip/lm4/lpc.c b/chip/lm4/lpc.c
index cc77984638..7563fe1875 100644
--- a/chip/lm4/lpc.c
+++ b/chip/lm4/lpc.c
@@ -801,7 +801,7 @@ DECLARE_HOOK(HOOK_CHIPSET_RESUME, lpc_resume, HOOK_PRIO_DEFAULT);
 void lpc_task(void)
 {
 	while (1) {
-		usleep(250000);
+		msleep(250);
 		/*
 		 * Make sure pending LPC interrupts have been processed.
 		 * This works around a LM4 bug where host writes sometimes
diff --git a/chip/lm4/mock_pwm.c b/chip/lm4/mock_pwm.c
index c7f8fabe0f..b269b8f116 100644
--- a/chip/lm4/mock_pwm.c
+++ b/chip/lm4/mock_pwm.c
@@ -65,5 +65,5 @@ void pwm_task(void)
 {
 	/* Do nothing */
 	while (1)
-		usleep(5000000);
+		sleep(5);
 }
diff --git a/chip/lm4/power_button.c b/chip/lm4/power_button.c
index ede3c3d938..d3e130e8f7 100644
--- a/chip/lm4/power_button.c
+++ b/chip/lm4/power_button.c
@@ -41,17 +41,17 @@
  *     @S0   make code             break code
  */
 /* TODO: link to full power button / lid switch state machine description. */
-#define PWRBTN_DEBOUNCE_US 30000  /* Debounce time for power button */
-#define PWRBTN_DELAY_T0    32000  /* 32ms (PCH requires >16ms) */
-#define PWRBTN_DELAY_T1    (4000000 - PWRBTN_DELAY_T0)  /* 4 secs - t0 */
-#define PWRBTN_INITIAL_US  200000 /* Length of time to stretch initial power
-				   * button press to give chipset a chance to
-				   * wake up (~100ms) and react to the press
-				   * (~16ms).  Also used as pulse length for
-				   * simulated power button presses when the
-				   * system is off. */
-
-#define LID_DEBOUNCE_US    30000  /* Debounce time for lid switch */
+#define PWRBTN_DEBOUNCE_US (30 * MSEC)  /* Debounce time for power button */
+#define PWRBTN_DELAY_T0    (32 * MSEC)  /* 32ms (PCH requires >16ms) */
+#define PWRBTN_DELAY_T1    (4 * SECOND - PWRBTN_DELAY_T0)  /* 4 secs - t0 */
+/*
+ * Length of time to stretch initial power button press to give chipset a
+ * chance to wake up (~100ms) and react to the press (~16ms).  Also used as
+ * pulse length for simulated power button presses when the system is off.
+ */
+#define PWRBTN_INITIAL_US  (200 * MSEC)
+
+#define LID_DEBOUNCE_US    (30 * MSEC)  /* Debounce time for lid switch */
 
 enum power_button_state {
 	/* Button up; state machine idle */
@@ -591,7 +591,7 @@ void power_button_interrupt(enum gpio_signal signal)
 
 static int command_powerbtn(int argc, char **argv)
 {
-	int ms = PWRBTN_INITIAL_US / 1000;  /* Press duration in ms */
+	int ms = PWRBTN_INITIAL_US / MSEC;  /* Press duration in ms */
 	char *e;
 
 	if (argc > 1) {
@@ -605,7 +605,7 @@ static int command_powerbtn(int argc, char **argv)
 	tdebounce_pwr = get_time().val + PWRBTN_DEBOUNCE_US;
 	task_wake(TASK_ID_POWERBTN);
 
-	usleep(ms * 1000);
+	msleep(ms);
 
 	ccprintf("Simulating power button release.\n");
 	simulate_power_pressed = 0;
diff --git a/chip/lm4/pwm.c b/chip/lm4/pwm.c
index 372e008943..e3f359c389 100644
--- a/chip/lm4/pwm.c
+++ b/chip/lm4/pwm.c
@@ -199,7 +199,7 @@ void pwm_task(void)
 			mapped[0] = pwm_get_fan_rpm();
 
 		/* Update about once a second */
-		usleep(1000000);
+		sleep(1);
 	}
 }
 
diff --git a/chip/stm32/dma.h b/chip/stm32/dma.h
index c9832fcfe3..4aed23ff05 100644
--- a/chip/stm32/dma.h
+++ b/chip/stm32/dma.h
@@ -91,7 +91,7 @@ enum {
 #define DMA_PSIZE_WORD		(2 << 8)
 
 #define DMA_POLLING_INTERVAL_US	100	/* us */
-#define DMA_TRANSFER_TIMEOUT_US	100000	/* us */
+#define DMA_TRANSFER_TIMEOUT_US	(100 * MSEC) /* us */
 
 /*
  * Certain DMA channels must be used for certain peripherals and transfer
diff --git a/chip/stm32/flash-stm32f100.c b/chip/stm32/flash-stm32f100.c
index 0801066b9d..52e267255d 100644
--- a/chip/stm32/flash-stm32f100.c
+++ b/chip/stm32/flash-stm32f100.c
@@ -17,8 +17,6 @@
 #include "util.h"
 #include "watchdog.h"
 
-#define US_PER_SECOND 1000000
-
 /*
  * Approximate number of CPU cycles per iteration of the loop when polling
  * the flash status
@@ -28,7 +26,7 @@
 /* Flash page programming timeout.  This is 2x the datasheet max. */
 #define FLASH_TIMEOUT_US 16000
 #define FLASH_TIMEOUT_LOOP \
-	(FLASH_TIMEOUT_US * (CPU_CLOCK / US_PER_SECOND) / CYCLE_PER_FLASH_LOOP)
+	(FLASH_TIMEOUT_US * (CPU_CLOCK / SECOND) / CYCLE_PER_FLASH_LOOP)
 
 /* Flash unlocking keys */
 #define KEY1    0x45670123
diff --git a/chip/stm32/flash-stm32l15x.c b/chip/stm32/flash-stm32l15x.c
index 98d1d7b2d6..cbe7953797 100644
--- a/chip/stm32/flash-stm32l15x.c
+++ b/chip/stm32/flash-stm32l15x.c
@@ -13,8 +13,6 @@
 #include "util.h"
 #include "watchdog.h"
 
-#define US_PER_SECOND 1000000
-
 /*
  * Approximate number of CPU cycles per iteration of the loop when polling
  * the flash status.
@@ -24,7 +22,7 @@
 /* Flash page programming timeout.  This is 2x the datasheet max. */
 #define FLASH_TIMEOUT_US 16000
 #define FLASH_TIMEOUT_LOOP \
-	(FLASH_TIMEOUT_US * (CPU_CLOCK / US_PER_SECOND) / CYCLE_PER_FLASH_LOOP)
+	(FLASH_TIMEOUT_US * (CPU_CLOCK / SECOND) / CYCLE_PER_FLASH_LOOP)
 
 /* Flash unlocking keys */
 #define PEKEY1  0x89ABCDEF
diff --git a/chip/stm32/hwtimer.c b/chip/stm32/hwtimer.c
index 0fe2168f55..3a58e9dcd1 100644
--- a/chip/stm32/hwtimer.c
+++ b/chip/stm32/hwtimer.c
@@ -5,20 +5,16 @@
 
 /* Hardware timers driver */
 
-#include <stdint.h>
-
-#include "board.h"
 #include "common.h"
 #include "hwtimer.h"
 #include "panic.h"
 #include "registers.h"
 #include "task.h"
+#include "timer.h"
 #include "watchdog.h"
 
-#define US_PER_SECOND 1000000
-
 /* Divider to get microsecond for the clock */
-#define CLOCKSOURCE_DIVIDER (CPU_CLOCK/US_PER_SECOND)
+#define CLOCKSOURCE_DIVIDER (CPU_CLOCK / SECOND)
 
 #ifdef CHIP_VARIANT_stm32f100
 #define TIM_WD_IRQ	STM32_IRQ_TIM1_UP_TIM16
@@ -47,10 +43,10 @@ void __hw_clock_event_set(uint32_t deadline)
 		STM32_TIM_DIER(3) |= 2;
 	}
 	/*
-	 * In the unlikely case where the MSB on TIM3 has increased and
-	 * matched the deadline MSB before we set the match interrupt,
-	 * as the STM hardware timer won't trigger an interrupt, we fall back
-	 * to the following LSB event code to set another interrupt.
+	 * In the unlikely case where the MSB on TIM3 has increased and matched
+	 * the deadline MSB before we set the match interrupt, as the STM
+	 * hardware timer won't trigger an interrupt, we fall back to the
+	 * following LSB event code to set another interrupt.
 	 */
 	if ((deadline >> 16) == STM32_TIM_CNT(3)) {
 		/* we can set a match on the LSB only */
@@ -64,10 +60,10 @@ void __hw_clock_event_set(uint32_t deadline)
 		STM32_TIM_DIER(4) |= 2;
 	}
 	/*
-	 * if the LSB deadline is already in the past and won't trigger
-	 * an interrupt, the common code in process_timers will deal with
-	 * the expired timer and automatically set the next deadline, we
-	 * don't need to do anything here.
+	 * If the LSB deadline is already in the past and won't trigger an
+	 * interrupt, the common code in process_timers will deal with the
+	 * expired timer and automatically set the next deadline, we don't need
+	 * to do anything here.
 	 */
 }
 
@@ -88,7 +84,7 @@ uint32_t __hw_clock_source_read(void)
 	uint32_t hi;
 	uint32_t lo;
 
-	/* ensure the two half-words are coherent */
+	/* Ensure the two half-words are coherent */
 	do {
 		hi = STM32_TIM_CNT(3);
 		lo = STM32_TIM_CNT(4);
@@ -107,7 +103,7 @@ static void __hw_clock_source_irq(void)
 {
 	uint32_t stat_tim3 = STM32_TIM_SR(3);
 
-	/* clear status */
+	/* Clear status */
 	STM32_TIM_SR(4) = 0;
 	STM32_TIM_SR(3) = 0;
 
@@ -176,10 +172,9 @@ int __hw_clock_source_init(uint32_t start_t)
 }
 
 /*
- * We don't have TIM1 on STM32L, so don't support this function for now.
- * TIM5 doesn't appear to exist in either variant, and TIM9 cannot be
- * triggered as a slave from TIM4. We could perhaps use TIM9 as our
- * fast counter on STM32L.
+ * We don't have TIM1 on STM32L, so don't support this function for now.  TIM5
+ * doesn't appear to exist in either variant, and TIM9 cannot be triggered as a
+ * slave from TIM4. We could perhaps use TIM9 as our fast counter on STM32L.
  */
 #ifdef CHIP_VARIANT_stm32f100
 
@@ -233,11 +228,10 @@ void hwtimer_setup_watchdog(void)
 	timer->smcr = 0x0037;
 
 	/*
-	 * The auto-reload value is based on the period between rollovers
-	 * for TIM4. Since TIM4 runs at 1MHz, it will overflow in 65.536ms.
-	 * We divide our required watchdog period by this amount to obtain
-	 * the number of times TIM4 can overflow before we generate an
-	 * interrupt.
+	 * The auto-reload value is based on the period between rollovers for
+	 * TIM4. Since TIM4 runs at 1MHz, it will overflow in 65.536ms.  We
+	 * divide our required watchdog period by this amount to obtain the
+	 * number of times TIM4 can overflow before we generate an interrupt.
 	 */
 	timer->arr = timer->cnt = WATCHDOG_PERIOD_MS * 1000 / (1 << 16);
 
diff --git a/chip/stm32/i2c.c b/chip/stm32/i2c.c
index 4c83ad9678..b42f415273 100644
--- a/chip/stm32/i2c.c
+++ b/chip/stm32/i2c.c
@@ -28,10 +28,10 @@
 #define I2C_FREQ 100000 /* Hz */
 
 /* I2C bit period in microseconds */
-#define I2C_PERIOD_US (1000000 / I2C_FREQ)
+#define I2C_PERIOD_US (SECOND / I2C_FREQ)
 
 /* Clock divider for I2C controller */
-#define I2C_CCR (CPU_CLOCK/(2 * I2C_FREQ))
+#define I2C_CCR (CPU_CLOCK / (2 * I2C_FREQ))
 
 /*
  * Transmit timeout in microseconds
@@ -41,8 +41,8 @@
  * ...but we're going to keep the timeout to make sure we're robust.  It may in
  * fact be needed if the host resets itself mid-read.
  */
-#define I2C_TX_TIMEOUT_SLAVE	100000 /* us */
-#define I2C_TX_TIMEOUT_MASTER	10000  /* us */
+#define I2C_TX_TIMEOUT_SLAVE	(100 * MSEC)
+#define I2C_TX_TIMEOUT_MASTER	(10 * MSEC)
 
 /*
  * We delay 5us in bitbang mode.  That gives us 5us low and 5us high or
diff --git a/chip/stm32/power_led.c b/chip/stm32/power_led.c
index 09d9d426cd..f5448c0b82 100644
--- a/chip/stm32/power_led.c
+++ b/chip/stm32/power_led.c
@@ -22,8 +22,8 @@
 #include "timer.h"
 #include "util.h"
 
-#define LED_STATE_TIMEOUT_MIN	15000	/* minimum of 15ms per step */
-#define LED_HOLD_TIME		330000	/* hold for 330ms at min/max */
+#define LED_STATE_TIMEOUT_MIN	(15 * MSEC)  /* Minimum of 15ms per step */
+#define LED_HOLD_TIME		(330 * MSEC) /* Hold for 330ms at min/max */
 #define LED_STEP_PERCENT	4	/* incremental value of each step */
 
 static enum powerled_state led_state = POWERLED_STATE_ON;