diff options
| author | Gwendal Grignou <gwendal@chromium.org> | 2019-03-11 16:07:55 -0700 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2019-03-26 04:42:56 -0700 |
| commit | ac77140b7f4f42075d2377fc9d956a636b05aacf (patch) | |
| tree | c64c6a30916ff741a2ab235141f7bd071cd54483 /chip | |
| parent | bb266fc26fc05d4ab22de6ad7bce5b477c9f9140 (diff) | |
| download | chrome-ec-ac77140b7f4f42075d2377fc9d956a636b05aacf.tar.gz | |
common: bit change 1 << constants with BIT(constants)
Mechanical replacement of bit operation where operand is a constant.
More bit operation exist, but prone to errors.
Reveal a bug in npcx:
chip/npcx/system-npcx7.c:114:54: error: conversion from 'long unsigned int' to 'uint8_t' {aka 'volatile unsigned char'} changes value from '16777215' to '255' [-Werror=overflow]
BUG=None
BRANCH=None
TEST=None
Change-Id: I006614026143fa180702ac0d1cc2ceb1b3c6eeb0
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1518660
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Diffstat (limited to 'chip')
67 files changed, 345 insertions, 345 deletions
diff --git a/chip/g/alerts.c b/chip/g/alerts.c index 6cfb936b9c..b53045ccaf 100644 --- a/chip/g/alerts.c +++ b/chip/g/alerts.c @@ -260,7 +260,7 @@ static int alert_intr_status(int alert) int reg = alert / 32; int offset = alert % 32; - return !!(*INTR_STATUS_ADDR[reg] & (1 << offset)); + return !!(*INTR_STATUS_ADDR[reg] & BIT(offset)); } #ifdef CONFIG_BOARD_ID_SUPPORT @@ -300,7 +300,7 @@ static void command_alerts_list(void) if (fuse == BROM_FWBIT_APPLYSEC_UNKNOWN) fuse_status = '?'; - else if (fuses & (1 << fuse)) + else if (fuses & BIT(fuse)) fuse_status = '+'; else fuse_status = '#'; diff --git a/chip/g/board_space.h b/chip/g/board_space.h index 90b6c02287..1884a5c74c 100644 --- a/chip/g/board_space.h +++ b/chip/g/board_space.h @@ -37,7 +37,7 @@ struct sn_data { /* Number of bits reserved for RMA counter */ #define RMA_COUNT_BITS 7 /* Value used to indicate device has been RMA'd */ -#define RMA_INDICATOR ((uint8_t) ~(1 << RMA_COUNT_BITS)) +#define RMA_INDICATOR ((uint8_t) ~BIT(RMA_COUNT_BITS)) /* Info1 Board space contents. */ struct info1_board_space { diff --git a/chip/g/flash_config.h b/chip/g/flash_config.h index 09ddd872d5..d1bec36871 100644 --- a/chip/g/flash_config.h +++ b/chip/g/flash_config.h @@ -15,9 +15,9 @@ #define FLASH_INFO_MANUFACTURE_STATE_SIZE 0x200 -#define FLASH_REGION_EN_ALL ((1 << GC_GLOBALSEC_FLASH_REGION0_CTRL_EN_LSB) |\ - (1 << GC_GLOBALSEC_FLASH_REGION0_CTRL_RD_EN_LSB) |\ - (1 << GC_GLOBALSEC_FLASH_REGION0_CTRL_WR_EN_LSB)) +#define FLASH_REGION_EN_ALL (BIT(GC_GLOBALSEC_FLASH_REGION0_CTRL_EN_LSB) |\ + BIT(GC_GLOBALSEC_FLASH_REGION0_CTRL_RD_EN_LSB) |\ + BIT(GC_GLOBALSEC_FLASH_REGION0_CTRL_WR_EN_LSB)) /* * The below structure describes a single flash region (the hardware supports diff --git a/chip/g/pmu.c b/chip/g/pmu.c index a324e6cee7..a434a2bde5 100644 --- a/chip/g/pmu.c +++ b/chip/g/pmu.c @@ -22,7 +22,7 @@ void pmu_clock_en(uint32_t periph) { if (periph <= 31) - GR_PMU_PERICLKSET0 = (1 << periph); + GR_PMU_PERICLKSET0 = BIT(periph); else GR_PMU_PERICLKSET1 = (1 << (periph - 32)); } @@ -34,7 +34,7 @@ void pmu_clock_en(uint32_t periph) void pmu_clock_dis(uint32_t periph) { if (periph <= 31) - GR_PMU_PERICLKCLR0 = (1 << periph); + GR_PMU_PERICLKCLR0 = BIT(periph); else GR_PMU_PERICLKCLR1 = (1 << (periph - 32)); } diff --git a/chip/g/polling_uart.c b/chip/g/polling_uart.c index b1e4c4e0e3..e28abc2344 100644 --- a/chip/g/polling_uart.c +++ b/chip/g/polling_uart.c @@ -7,7 +7,7 @@ #include "registers.h" #include "uart.h" -#define UART_NCO ((16 * (1 << UART_NCO_WIDTH) * \ +#define UART_NCO ((16 * BIT(UART_NCO_WIDTH) * \ (long long)CONFIG_UART_BAUD_RATE) / PCLK_FREQ) /* 115200N81 uart0, TX on A0, RX on A1 */ diff --git a/chip/g/registers.h b/chip/g/registers.h index 9127802db3..0e69b75eaa 100644 --- a/chip/g/registers.h +++ b/chip/g/registers.h @@ -408,8 +408,8 @@ static inline int x_timehs_addr(unsigned int module, unsigned int timer, #define USB_TX_DPO BIT(1) #define USB_TX_DMO BIT(0) -#define GAHBCFG_DMA_EN (1 << GC_USB_GAHBCFG_DMAEN_LSB) -#define GAHBCFG_GLB_INTR_EN (1 << GC_USB_GAHBCFG_GLBLINTRMSK_LSB) +#define GAHBCFG_DMA_EN BIT(GC_USB_GAHBCFG_DMAEN_LSB) +#define GAHBCFG_GLB_INTR_EN BIT(GC_USB_GAHBCFG_GLBLINTRMSK_LSB) #define GAHBCFG_HBSTLEN_INCR4 (3 << GC_USB_GAHBCFG_HBSTLEN_LSB) #define GAHBCFG_NP_TXF_EMP_LVL (1 << GC_USB_GAHBCFG_NPTXFEMPLVL_LSB) @@ -418,86 +418,86 @@ static inline int x_timehs_addr(unsigned int module, unsigned int timer, #define GUSBCFG_USBTRDTIM(n) (((n) << GC_USB_GUSBCFG_USBTRDTIM_LSB) \ & GC_USB_GUSBCFG_USBTRDTIM_MASK) #define GUSBCFG_PHYSEL_HS (0 << GC_USB_GUSBCFG_PHYSEL_LSB) -#define GUSBCFG_PHYSEL_FS (1 << GC_USB_GUSBCFG_PHYSEL_LSB) +#define GUSBCFG_PHYSEL_FS BIT(GC_USB_GUSBCFG_PHYSEL_LSB) #define GUSBCFG_FSINTF_6PIN (0 << GC_USB_GUSBCFG_FSINTF_LSB) -#define GUSBCFG_FSINTF_3PIN (1 << GC_USB_GUSBCFG_FSINTF_LSB) -#define GUSBCFG_PHYIF16 (1 << GC_USB_GUSBCFG_PHYIF_LSB) +#define GUSBCFG_FSINTF_3PIN BIT(GC_USB_GUSBCFG_FSINTF_LSB) +#define GUSBCFG_PHYIF16 BIT(GC_USB_GUSBCFG_PHYIF_LSB) #define GUSBCFG_PHYIF8 (0 << GC_USB_GUSBCFG_PHYIF_LSB) -#define GUSBCFG_ULPI (1 << GC_USB_GUSBCFG_ULPI_UTMI_SEL_LSB) +#define GUSBCFG_ULPI BIT(GC_USB_GUSBCFG_ULPI_UTMI_SEL_LSB) #define GUSBCFG_UTMI (0 << GC_USB_GUSBCFG_ULPI_UTMI_SEL_LSB) -#define GRSTCTL_CSFTRST (1 << GC_USB_GRSTCTL_CSFTRST_LSB) -#define GRSTCTL_AHBIDLE (1 << GC_USB_GRSTCTL_AHBIDLE_LSB) -#define GRSTCTL_TXFFLSH (1 << GC_USB_GRSTCTL_TXFFLSH_LSB) -#define GRSTCTL_RXFFLSH (1 << GC_USB_GRSTCTL_RXFFLSH_LSB) +#define GRSTCTL_CSFTRST BIT(GC_USB_GRSTCTL_CSFTRST_LSB) +#define GRSTCTL_AHBIDLE BIT(GC_USB_GRSTCTL_AHBIDLE_LSB) +#define GRSTCTL_TXFFLSH BIT(GC_USB_GRSTCTL_TXFFLSH_LSB) +#define GRSTCTL_RXFFLSH BIT(GC_USB_GRSTCTL_RXFFLSH_LSB) #define GRSTCTL_TXFNUM(n) (((n) << GC_USB_GRSTCTL_TXFNUM_LSB) & GC_USB_GRSTCTL_TXFNUM_MASK) -#define DCFG_DEVSPD_FS (1 << GC_USB_DCFG_DEVSPD_LSB) +#define DCFG_DEVSPD_FS BIT(GC_USB_DCFG_DEVSPD_LSB) #define DCFG_DEVSPD_FS48 (3 << GC_USB_DCFG_DEVSPD_LSB) #define DCFG_DEVADDR(a) (((a) << GC_USB_DCFG_DEVADDR_LSB) & GC_USB_DCFG_DEVADDR_MASK) -#define DCFG_DESCDMA (1 << GC_USB_DCFG_DESCDMA_LSB) +#define DCFG_DESCDMA BIT(GC_USB_DCFG_DESCDMA_LSB) -#define DCTL_SFTDISCON (1 << GC_USB_DCTL_SFTDISCON_LSB) -#define DCTL_CGOUTNAK (1 << GC_USB_DCTL_CGOUTNAK_LSB) -#define DCTL_CGNPINNAK (1 << GC_USB_DCTL_CGNPINNAK_LSB) -#define DCTL_PWRONPRGDONE (1 << GC_USB_DCTL_PWRONPRGDONE_LSB) +#define DCTL_SFTDISCON BIT(GC_USB_DCTL_SFTDISCON_LSB) +#define DCTL_CGOUTNAK BIT(GC_USB_DCTL_CGOUTNAK_LSB) +#define DCTL_CGNPINNAK BIT(GC_USB_DCTL_CGNPINNAK_LSB) +#define DCTL_PWRONPRGDONE BIT(GC_USB_DCTL_PWRONPRGDONE_LSB) /* Device Endpoint Common IN Interrupt Mask bits */ -#define DIEPMSK_AHBERRMSK (1 << GC_USB_DIEPMSK_AHBERRMSK_LSB) -#define DIEPMSK_BNAININTRMSK (1 << GC_USB_DIEPMSK_BNAININTRMSK_LSB) -#define DIEPMSK_EPDISBLDMSK (1 << GC_USB_DIEPMSK_EPDISBLDMSK_LSB) -#define DIEPMSK_INEPNAKEFFMSK (1 << GC_USB_DIEPMSK_INEPNAKEFFMSK_LSB) -#define DIEPMSK_INTKNEPMISMSK (1 << GC_USB_DIEPMSK_INTKNEPMISMSK_LSB) -#define DIEPMSK_INTKNTXFEMPMSK (1 << GC_USB_DIEPMSK_INTKNTXFEMPMSK_LSB) -#define DIEPMSK_NAKMSK (1 << GC_USB_DIEPMSK_NAKMSK_LSB) -#define DIEPMSK_TIMEOUTMSK (1 << GC_USB_DIEPMSK_TIMEOUTMSK_LSB) -#define DIEPMSK_TXFIFOUNDRNMSK (1 << GC_USB_DIEPMSK_TXFIFOUNDRNMSK_LSB) -#define DIEPMSK_XFERCOMPLMSK (1 << GC_USB_DIEPMSK_XFERCOMPLMSK_LSB) +#define DIEPMSK_AHBERRMSK BIT(GC_USB_DIEPMSK_AHBERRMSK_LSB) +#define DIEPMSK_BNAININTRMSK BIT(GC_USB_DIEPMSK_BNAININTRMSK_LSB) +#define DIEPMSK_EPDISBLDMSK BIT(GC_USB_DIEPMSK_EPDISBLDMSK_LSB) +#define DIEPMSK_INEPNAKEFFMSK BIT(GC_USB_DIEPMSK_INEPNAKEFFMSK_LSB) +#define DIEPMSK_INTKNEPMISMSK BIT(GC_USB_DIEPMSK_INTKNEPMISMSK_LSB) +#define DIEPMSK_INTKNTXFEMPMSK BIT(GC_USB_DIEPMSK_INTKNTXFEMPMSK_LSB) +#define DIEPMSK_NAKMSK BIT(GC_USB_DIEPMSK_NAKMSK_LSB) +#define DIEPMSK_TIMEOUTMSK BIT(GC_USB_DIEPMSK_TIMEOUTMSK_LSB) +#define DIEPMSK_TXFIFOUNDRNMSK BIT(GC_USB_DIEPMSK_TXFIFOUNDRNMSK_LSB) +#define DIEPMSK_XFERCOMPLMSK BIT(GC_USB_DIEPMSK_XFERCOMPLMSK_LSB) /* Device Endpoint Common OUT Interrupt Mask bits */ -#define DOEPMSK_AHBERRMSK (1 << GC_USB_DOEPMSK_AHBERRMSK_LSB) -#define DOEPMSK_BBLEERRMSK (1 << GC_USB_DOEPMSK_BBLEERRMSK_LSB) -#define DOEPMSK_BNAOUTINTRMSK (1 << GC_USB_DOEPMSK_BNAOUTINTRMSK_LSB) -#define DOEPMSK_EPDISBLDMSK (1 << GC_USB_DOEPMSK_EPDISBLDMSK_LSB) -#define DOEPMSK_NAKMSK (1 << GC_USB_DOEPMSK_NAKMSK_LSB) -#define DOEPMSK_NYETMSK (1 << GC_USB_DOEPMSK_NYETMSK_LSB) -#define DOEPMSK_OUTPKTERRMSK (1 << GC_USB_DOEPMSK_OUTPKTERRMSK_LSB) -#define DOEPMSK_OUTTKNEPDISMSK (1 << GC_USB_DOEPMSK_OUTTKNEPDISMSK_LSB) -#define DOEPMSK_SETUPMSK (1 << GC_USB_DOEPMSK_SETUPMSK_LSB) -#define DOEPMSK_STSPHSERCVDMSK (1 << GC_USB_DOEPMSK_STSPHSERCVDMSK_LSB) -#define DOEPMSK_XFERCOMPLMSK (1 << GC_USB_DOEPMSK_XFERCOMPLMSK_LSB) +#define DOEPMSK_AHBERRMSK BIT(GC_USB_DOEPMSK_AHBERRMSK_LSB) +#define DOEPMSK_BBLEERRMSK BIT(GC_USB_DOEPMSK_BBLEERRMSK_LSB) +#define DOEPMSK_BNAOUTINTRMSK BIT(GC_USB_DOEPMSK_BNAOUTINTRMSK_LSB) +#define DOEPMSK_EPDISBLDMSK BIT(GC_USB_DOEPMSK_EPDISBLDMSK_LSB) +#define DOEPMSK_NAKMSK BIT(GC_USB_DOEPMSK_NAKMSK_LSB) +#define DOEPMSK_NYETMSK BIT(GC_USB_DOEPMSK_NYETMSK_LSB) +#define DOEPMSK_OUTPKTERRMSK BIT(GC_USB_DOEPMSK_OUTPKTERRMSK_LSB) +#define DOEPMSK_OUTTKNEPDISMSK BIT(GC_USB_DOEPMSK_OUTTKNEPDISMSK_LSB) +#define DOEPMSK_SETUPMSK BIT(GC_USB_DOEPMSK_SETUPMSK_LSB) +#define DOEPMSK_STSPHSERCVDMSK BIT(GC_USB_DOEPMSK_STSPHSERCVDMSK_LSB) +#define DOEPMSK_XFERCOMPLMSK BIT(GC_USB_DOEPMSK_XFERCOMPLMSK_LSB) /* Device Endpoint-n IN Interrupt Register bits */ -#define DIEPINT_AHBERR (1 << GC_USB_DIEPINT0_AHBERR_LSB) -#define DIEPINT_BBLEERR (1 << GC_USB_DIEPINT0_BBLEERR_LSB) -#define DIEPINT_BNAINTR (1 << GC_USB_DIEPINT0_BNAINTR_LSB) -#define DIEPINT_EPDISBLD (1 << GC_USB_DIEPINT0_EPDISBLD_LSB) -#define DIEPINT_INEPNAKEFF (1 << GC_USB_DIEPINT0_INEPNAKEFF_LSB) -#define DIEPINT_INTKNEPMIS (1 << GC_USB_DIEPINT0_INTKNEPMIS_LSB) -#define DIEPINT_INTKNTXFEMP (1 << GC_USB_DIEPINT0_INTKNTXFEMP_LSB) -#define DIEPINT_NAKINTRPT (1 << GC_USB_DIEPINT0_NAKINTRPT_LSB) -#define DIEPINT_NYETINTRPT (1 << GC_USB_DIEPINT0_NYETINTRPT_LSB) -#define DIEPINT_PKTDRPSTS (1 << GC_USB_DIEPINT0_PKTDRPSTS_LSB) -#define DIEPINT_TIMEOUT (1 << GC_USB_DIEPINT0_TIMEOUT_LSB) -#define DIEPINT_TXFEMP (1 << GC_USB_DIEPINT0_TXFEMP_LSB) -#define DIEPINT_TXFIFOUNDRN (1 << GC_USB_DIEPINT0_TXFIFOUNDRN_LSB) -#define DIEPINT_XFERCOMPL (1 << GC_USB_DIEPINT0_XFERCOMPL_LSB) +#define DIEPINT_AHBERR BIT(GC_USB_DIEPINT0_AHBERR_LSB) +#define DIEPINT_BBLEERR BIT(GC_USB_DIEPINT0_BBLEERR_LSB) +#define DIEPINT_BNAINTR BIT(GC_USB_DIEPINT0_BNAINTR_LSB) +#define DIEPINT_EPDISBLD BIT(GC_USB_DIEPINT0_EPDISBLD_LSB) +#define DIEPINT_INEPNAKEFF BIT(GC_USB_DIEPINT0_INEPNAKEFF_LSB) +#define DIEPINT_INTKNEPMIS BIT(GC_USB_DIEPINT0_INTKNEPMIS_LSB) +#define DIEPINT_INTKNTXFEMP BIT(GC_USB_DIEPINT0_INTKNTXFEMP_LSB) +#define DIEPINT_NAKINTRPT BIT(GC_USB_DIEPINT0_NAKINTRPT_LSB) +#define DIEPINT_NYETINTRPT BIT(GC_USB_DIEPINT0_NYETINTRPT_LSB) +#define DIEPINT_PKTDRPSTS BIT(GC_USB_DIEPINT0_PKTDRPSTS_LSB) +#define DIEPINT_TIMEOUT BIT(GC_USB_DIEPINT0_TIMEOUT_LSB) +#define DIEPINT_TXFEMP BIT(GC_USB_DIEPINT0_TXFEMP_LSB) +#define DIEPINT_TXFIFOUNDRN BIT(GC_USB_DIEPINT0_TXFIFOUNDRN_LSB) +#define DIEPINT_XFERCOMPL BIT(GC_USB_DIEPINT0_XFERCOMPL_LSB) /* Device Endpoint-n OUT Interrupt Register bits */ -#define DOEPINT_AHBERR (1 << GC_USB_DOEPINT0_AHBERR_LSB) -#define DOEPINT_BACK2BACKSETUP (1 << GC_USB_DOEPINT0_BACK2BACKSETUP_LSB) -#define DOEPINT_BBLEERR (1 << GC_USB_DOEPINT0_BBLEERR_LSB) -#define DOEPINT_BNAINTR (1 << GC_USB_DOEPINT0_BNAINTR_LSB) -#define DOEPINT_EPDISBLD (1 << GC_USB_DOEPINT0_EPDISBLD_LSB) -#define DOEPINT_NAKINTRPT (1 << GC_USB_DOEPINT0_NAKINTRPT_LSB) -#define DOEPINT_NYETINTRPT (1 << GC_USB_DOEPINT0_NYETINTRPT_LSB) -#define DOEPINT_OUTPKTERR (1 << GC_USB_DOEPINT0_OUTPKTERR_LSB) -#define DOEPINT_OUTTKNEPDIS (1 << GC_USB_DOEPINT0_OUTTKNEPDIS_LSB) -#define DOEPINT_PKTDRPSTS (1 << GC_USB_DOEPINT0_PKTDRPSTS_LSB) -#define DOEPINT_SETUP (1 << GC_USB_DOEPINT0_SETUP_LSB) -#define DOEPINT_STSPHSERCVD (1 << GC_USB_DOEPINT0_STSPHSERCVD_LSB) -#define DOEPINT_STUPPKTRCVD (1 << GC_USB_DOEPINT0_STUPPKTRCVD_LSB) -#define DOEPINT_XFERCOMPL (1 << GC_USB_DOEPINT0_XFERCOMPL_LSB) +#define DOEPINT_AHBERR BIT(GC_USB_DOEPINT0_AHBERR_LSB) +#define DOEPINT_BACK2BACKSETUP BIT(GC_USB_DOEPINT0_BACK2BACKSETUP_LSB) +#define DOEPINT_BBLEERR BIT(GC_USB_DOEPINT0_BBLEERR_LSB) +#define DOEPINT_BNAINTR BIT(GC_USB_DOEPINT0_BNAINTR_LSB) +#define DOEPINT_EPDISBLD BIT(GC_USB_DOEPINT0_EPDISBLD_LSB) +#define DOEPINT_NAKINTRPT BIT(GC_USB_DOEPINT0_NAKINTRPT_LSB) +#define DOEPINT_NYETINTRPT BIT(GC_USB_DOEPINT0_NYETINTRPT_LSB) +#define DOEPINT_OUTPKTERR BIT(GC_USB_DOEPINT0_OUTPKTERR_LSB) +#define DOEPINT_OUTTKNEPDIS BIT(GC_USB_DOEPINT0_OUTTKNEPDIS_LSB) +#define DOEPINT_PKTDRPSTS BIT(GC_USB_DOEPINT0_PKTDRPSTS_LSB) +#define DOEPINT_SETUP BIT(GC_USB_DOEPINT0_SETUP_LSB) +#define DOEPINT_STSPHSERCVD BIT(GC_USB_DOEPINT0_STSPHSERCVD_LSB) +#define DOEPINT_STUPPKTRCVD BIT(GC_USB_DOEPINT0_STUPPKTRCVD_LSB) +#define DOEPINT_XFERCOMPL BIT(GC_USB_DOEPINT0_XFERCOMPL_LSB) #define DXEPCTL_EPTYPE_CTRL (0 << GC_USB_DIEPCTL0_EPTYPE_LSB) #define DXEPCTL_EPTYPE_ISO (1 << GC_USB_DIEPCTL0_EPTYPE_LSB) @@ -505,14 +505,14 @@ static inline int x_timehs_addr(unsigned int module, unsigned int timer, #define DXEPCTL_EPTYPE_INT (3 << GC_USB_DIEPCTL0_EPTYPE_LSB) #define DXEPCTL_EPTYPE_MASK GC_USB_DIEPCTL0_EPTYPE_MASK #define DXEPCTL_TXFNUM(n) ((n) << GC_USB_DIEPCTL1_TXFNUM_LSB) -#define DXEPCTL_STALL (1 << GC_USB_DIEPCTL0_STALL_LSB) -#define DXEPCTL_CNAK (1 << GC_USB_DIEPCTL0_CNAK_LSB) -#define DXEPCTL_DPID (1 << GC_USB_DIEPCTL1_DPID_LSB) -#define DXEPCTL_SNAK (1 << GC_USB_DIEPCTL0_SNAK_LSB) -#define DXEPCTL_NAKSTS (1 << GC_USB_DIEPCTL0_NAKSTS_LSB) -#define DXEPCTL_EPENA (1 << GC_USB_DIEPCTL0_EPENA_LSB) -#define DXEPCTL_EPDIS (1 << GC_USB_DIEPCTL0_EPDIS_LSB) -#define DXEPCTL_USBACTEP (1 << GC_USB_DIEPCTL0_USBACTEP_LSB) +#define DXEPCTL_STALL BIT(GC_USB_DIEPCTL0_STALL_LSB) +#define DXEPCTL_CNAK BIT(GC_USB_DIEPCTL0_CNAK_LSB) +#define DXEPCTL_DPID BIT(GC_USB_DIEPCTL1_DPID_LSB) +#define DXEPCTL_SNAK BIT(GC_USB_DIEPCTL0_SNAK_LSB) +#define DXEPCTL_NAKSTS BIT(GC_USB_DIEPCTL0_NAKSTS_LSB) +#define DXEPCTL_EPENA BIT(GC_USB_DIEPCTL0_EPENA_LSB) +#define DXEPCTL_EPDIS BIT(GC_USB_DIEPCTL0_EPDIS_LSB) +#define DXEPCTL_USBACTEP BIT(GC_USB_DIEPCTL0_USBACTEP_LSB) #define DXEPCTL_MPS64 (0 << GC_USB_DIEPCTL0_MPS_LSB) #define DXEPCTL_MPS(cnt) ((cnt) << GC_USB_DIEPCTL1_MPS_LSB) #define DXEPCTL_SET_D0PID BIT(28) diff --git a/chip/g/uart_bitbang.c b/chip/g/uart_bitbang.c index 9f08340d3c..31bce8128a 100644 --- a/chip/g/uart_bitbang.c +++ b/chip/g/uart_bitbang.c @@ -213,7 +213,7 @@ static void uart_bitbang_write_char(char c) /* 8 data bits. */ ones = 0; for (i = 0; i < 8; i++) { - val = !!(c & (1 << i)); + val = !!(c & BIT(i)); gpio_set_level(bitbang_config.tx_gpio, val); /* Count 1's in order to handle parity bit. */ @@ -271,7 +271,7 @@ static int uart_bitbang_receive_char(uint8_t *rxed_char, uint32_t *next_tick) for (i = 0; i < 8; i++) { if (gpio_get_level(bitbang_config.rx_gpio)) { ones++; - rx_char |= (1 << i); + rx_char |= BIT(i); } wait_ticks(next_tick); } diff --git a/chip/g/uartn.c b/chip/g/uartn.c index 8f14f3c54e..da85c5cb0a 100644 --- a/chip/g/uartn.c +++ b/chip/g/uartn.c @@ -144,7 +144,7 @@ int uartn_is_enabled(int uart) void uartn_init(int uart) { - long long setting = (16 * (1 << UART_NCO_WIDTH) * + long long setting = (16 * BIT(UART_NCO_WIDTH) * (long long)CONFIG_UART_BAUD_RATE / PCLK_FREQ); /* set frequency */ diff --git a/chip/g/usb.c b/chip/g/usb.c index 37fef3179d..27ffde40aa 100644 --- a/chip/g/usb.c +++ b/chip/g/usb.c @@ -136,7 +136,7 @@ static void showbits(uint32_t b) int i; for (i = 0; i < 32; i++) - if (b & (1 << i)) { + if (b & BIT(i)) { if (deezbits[i]) ccprintf(" %s", deezbits[i]); else @@ -1255,7 +1255,7 @@ void usb_save_suspended_state(void) /* Record the state the DATA PIDs toggling on each endpoint. */ for (i = 1; i < USB_EP_COUNT; i++) { if (GR_USB_DOEPCTL(i) & DXEPCTL_DPID) - pid |= (1 << i); + pid |= BIT(i); if (GR_USB_DIEPCTL(i) & DXEPCTL_DPID) pid |= (1 << (i + 16)); } @@ -1275,7 +1275,7 @@ void usb_restore_suspended_state(void) /* Restore the DATA PIDs on endpoints. */ pid = GREG32(PMU, PWRDN_SCRATCH19); for (i = 1; i < USB_EP_COUNT; i++) { - GR_USB_DOEPCTL(i) = pid & (1 << i) ? + GR_USB_DOEPCTL(i) = pid & BIT(i) ? DXEPCTL_SET_D1PID : DXEPCTL_SET_D0PID; GR_USB_DIEPCTL(i) = pid & (1 << (i + 16)) ? DXEPCTL_SET_D1PID : DXEPCTL_SET_D0PID; diff --git a/chip/host/config_chip.h b/chip/host/config_chip.h index 8cb8bba79c..8714b57891 100644 --- a/chip/host/config_chip.h +++ b/chip/host/config_chip.h @@ -44,7 +44,7 @@ extern char __host_flash[CONFIG_FLASH_SIZE]; /* Do NOT use common timer code which is designed for hardware counters. */ #undef CONFIG_COMMON_TIMER -#define GPIO_PIN(port, index) GPIO_##port, (1 << index) +#define GPIO_PIN(port, index) GPIO_##port, BIT(index) #define GPIO_PIN_MASK(p, m) .port = GPIO_##p, .mask = (m) #define I2C_PORT_COUNT 1 diff --git a/chip/host/usb_pd_phy.c b/chip/host/usb_pd_phy.c index dd16890e6b..c44b8eea02 100644 --- a/chip/host/usb_pd_phy.c +++ b/chip/host/usb_pd_phy.c @@ -259,7 +259,7 @@ static uint8_t decode_bmc(uint32_t val10) for (i = 0; i < 5; ++i) if (!!(val10 & (1 << (2 * i))) != !!(val10 & (1 << (2 * i + 1)))) - ret |= (1 << i); + ret |= BIT(i); return ret; } diff --git a/chip/ish/hwtimer.c b/chip/ish/hwtimer.c index 63c9dcde0a..79a48783d9 100644 --- a/chip/ish/hwtimer.c +++ b/chip/ish/hwtimer.c @@ -77,7 +77,7 @@ static inline uint32_t scale_ticks2us(uint64_t ticks) #elif defined(CHIP_FAMILY_ISH4) || defined(CHIP_FAMILY_ISH5) #define CLOCK_SCALE_BITS 15 -BUILD_ASSERT((1 << CLOCK_SCALE_BITS) == ISH_HPET_CLK_FREQ); +BUILD_ASSERT(BIT(CLOCK_SCALE_BITS) == ISH_HPET_CLK_FREQ); static inline uint32_t scale_us2ticks(uint32_t us) { @@ -204,7 +204,7 @@ void __hw_clock_source_set(uint32_t ts) static void __hw_clock_source_irq(int timer_id) { /* Clear interrupt */ - HPET_INTR_CLEAR = (1 << timer_id); + HPET_INTR_CLEAR = BIT(timer_id); /* * If IRQ is from timer 0, 2^32 us have elapsed (i.e. OS timer diff --git a/chip/ish/i2c.c b/chip/ish/i2c.c index 525bee3732..79f0dd13de 100644 --- a/chip/ish/i2c.c +++ b/chip/ish/i2c.c @@ -335,7 +335,7 @@ int chip_i2c_xfer(int port, int slave_addr, const uint8_t *out, int out_size, if (in_size > (ISH_I2C_FIFO_SIZE - out_size)) { while ((i2c_mmio_read(ctx->base, IC_STATUS) & - (1 << IC_STATUS_TFE)) == 0) { + BIT(IC_STATUS_TFE)) == 0) { if (__hw_clock_source_read() >= expire_ts) { ctx->error_flag = 1; @@ -398,7 +398,7 @@ int chip_i2c_xfer(int port, int slave_addr, const uint8_t *out, int out_size, expire_ts = __hw_clock_source_read() + I2C_TSC_TIMEOUT; while (i2c_mmio_read(ctx->base, IC_STATUS) & - (1 << IC_STATUS_MASTER_ACTIVITY)) { + BIT(IC_STATUS_MASTER_ACTIVITY)) { if (__hw_clock_source_read() >= expire_ts) { ctx->error_flag = 1; diff --git a/chip/ish/ipc_heci.c b/chip/ish/ipc_heci.c index b7c471e802..41eff37667 100644 --- a/chip/ish/ipc_heci.c +++ b/chip/ish/ipc_heci.c @@ -93,7 +93,7 @@ #define IPC_DB_CMD_MASK (IPC_DB_CMD_FIELD << IPC_DB_CMD_SHIFT) #define IPC_DB_BUSY_SHIFT 31 -#define IPC_DB_BUSY_MASK (1 << IPC_DB_BUSY_SHIFT) +#define IPC_DB_BUSY_MASK BIT(IPC_DB_BUSY_SHIFT) #define IPC_DB_MSG_LENGTH(drbl) \ (((drbl) & IPC_DB_MSG_LENGTH_MASK) >> IPC_DB_MSG_LENGTH_SHIFT) diff --git a/chip/ish/ish_i2c.h b/chip/ish/ish_i2c.h index 2b88524fda..b9b284c7c5 100644 --- a/chip/ish/ish_i2c.h +++ b/chip/ish/ish_i2c.h @@ -169,7 +169,7 @@ enum { /* IC_ENABLE_STATUS_VALUES */ IC_EN_DISABLED_VAL = 0, IC_EN_DISABLED = (IC_EN_DISABLED_VAL << IC_EN_OFFSET), - IC_EN_MASK = (1 << IC_EN_OFFSET), + IC_EN_MASK = BIT(IC_EN_OFFSET), /* IC_TX_ABRT_SOURCE bits */ ABRT_7B_ADDR_NOACK = 1, }; diff --git a/chip/ish/uart_defs.h b/chip/ish/uart_defs.h index 86c6748f06..6a04557c58 100644 --- a/chip/ish/uart_defs.h +++ b/chip/ish/uart_defs.h @@ -191,7 +191,7 @@ #define UART_ISH_INPUT_FREQ MHZ(100) #endif #define UART_DEFAULT_BAUD_RATE 115200 -#define UART_STATE_CG (1 << UART_OP_CG) +#define UART_STATE_CG BIT(UART_OP_CG) enum UART_PORT { UART_PORT_0, diff --git a/chip/it83xx/adc.c b/chip/it83xx/adc.c index 71f92c44e9..0dadca3875 100644 --- a/chip/it83xx/adc.c +++ b/chip/it83xx/adc.c @@ -105,7 +105,7 @@ static void adc_disable_channel(int ch) static int adc_data_valid(enum chip_adc_channel adc_ch) { return (adc_ch <= CHIP_ADC_CH7) ? - (IT83XX_ADC_ADCDVSTS & (1 << adc_ch)) : + (IT83XX_ADC_ADCDVSTS & BIT(adc_ch)) : (IT83XX_ADC_ADCDVSTS2 & (1 << (adc_ch - CHIP_ADC_CH13))); } @@ -138,7 +138,7 @@ int adc_read_channel(enum adc_channel ch) /* W/C data valid flag */ if (adc_ch <= CHIP_ADC_CH7) - IT83XX_ADC_ADCDVSTS = (1 << adc_ch); + IT83XX_ADC_ADCDVSTS = BIT(adc_ch); else IT83XX_ADC_ADCDVSTS2 = (1 << (adc_ch - CHIP_ADC_CH13)); diff --git a/chip/it83xx/config_chip.h b/chip/it83xx/config_chip.h index aed0478b35..2e71fb3ef6 100644 --- a/chip/it83xx/config_chip.h +++ b/chip/it83xx/config_chip.h @@ -160,7 +160,7 @@ /* Chip needs to do custom pre-init */ #define CONFIG_CHIP_PRE_INIT -#define GPIO_PIN(port, index) GPIO_##port, (1 << index) +#define GPIO_PIN(port, index) GPIO_##port, BIT(index) #define GPIO_PIN_MASK(p, m) .port = GPIO_##p, .mask = (m) #endif /* __CROS_EC_CONFIG_CHIP_H */ diff --git a/chip/it83xx/espi.c b/chip/it83xx/espi.c index 9e68eedf00..972ac6c146 100644 --- a/chip/it83xx/espi.c +++ b/chip/it83xx/espi.c @@ -396,7 +396,7 @@ void espi_vw_interrupt(void) task_clear_pending_irq(IT83XX_IRQ_ESPI_VW); for (i = 0; i < ARRAY_SIZE(vw_isr_list); i++) { - if (vwidx_updated & (1 << i)) { + if (vwidx_updated & BIT(i)) { uint8_t idx_flag; idx_flag = IT83XX_ESPI_VWIDX(vw_isr_list[i].vw_index); @@ -551,7 +551,7 @@ void espi_interrupt(void) IT83XX_ESPI_ESGCTRL0 = espi_event; /* process espi interrupt events */ for (i = 0; i < ARRAY_SIZE(espi_isr); i++) { - if (espi_event & (1 << i)) + if (espi_event & BIT(i)) espi_isr[i](i); } /* diff --git a/chip/it83xx/gpio.c b/chip/it83xx/gpio.c index 5c390553ef..e5c63d4f95 100644 --- a/chip/it83xx/gpio.c +++ b/chip/it83xx/gpio.c @@ -437,7 +437,7 @@ static const char *get_gpio_string(const int port, const int mask) buffer[1] = '!'; for (i = 0; i < 8; ++i) { - if (mask & (1 << i)) { + if (mask & BIT(i)) { buffer[1] = i + '0'; break; } diff --git a/chip/it83xx/irq.c b/chip/it83xx/irq.c index fb2c0ee167..ee18050627 100644 --- a/chip/it83xx/irq.c +++ b/chip/it83xx/irq.c @@ -66,8 +66,8 @@ int chip_disable_irq(int irq) int group = irq / 8; int bit = irq % 8; - IT83XX_INTC_REG(irq_groups[group].ier_off) &= ~(1 << bit); - IT83XX_INTC_REG(IT83XX_INTC_EXT_IER_OFF(group)) &= ~(1 << bit); + IT83XX_INTC_REG(irq_groups[group].ier_off) &= ~BIT(bit); + IT83XX_INTC_REG(IT83XX_INTC_EXT_IER_OFF(group)) &= ~BIT(bit); return -1; /* we don't want to mask other IRQs */ } diff --git a/chip/it83xx/keyboard_raw.c b/chip/it83xx/keyboard_raw.c index d6d01e1247..225063f90a 100644 --- a/chip/it83xx/keyboard_raw.c +++ b/chip/it83xx/keyboard_raw.c @@ -77,7 +77,7 @@ test_mockable void keyboard_raw_drive_column(int col) mask = 0; /* Assert a single output */ else - mask = 0xffff ^ (1 << col); + mask = 0xffff ^ BIT(col); #ifdef CONFIG_KEYBOARD_COL2_INVERTED /* KSO[2] is inverted. */ diff --git a/chip/lm4/config_chip.h b/chip/lm4/config_chip.h index 020a5d7c09..2456095aba 100644 --- a/chip/lm4/config_chip.h +++ b/chip/lm4/config_chip.h @@ -102,7 +102,7 @@ /* Chip needs to do custom pre-init */ #define CONFIG_CHIP_PRE_INIT -#define GPIO_PIN(port, index) GPIO_##port, (1 << index) +#define GPIO_PIN(port, index) GPIO_##port, BIT(index) #define GPIO_PIN_MASK(p, m) .port = GPIO_##p, .mask = (m) #endif /* __CROS_EC_CONFIG_CHIP_H */ diff --git a/chip/lm4/fan.c b/chip/lm4/fan.c index 39baa0a03e..c0eee330db 100644 --- a/chip/lm4/fan.c +++ b/chip/lm4/fan.c @@ -32,14 +32,14 @@ void fan_set_enabled(int ch, int enabled) { if (enabled) - LM4_FAN_FANCTL |= (1 << ch); + LM4_FAN_FANCTL |= BIT(ch); else - LM4_FAN_FANCTL &= ~(1 << ch); + LM4_FAN_FANCTL &= ~BIT(ch); } int fan_get_enabled(int ch) { - return (LM4_FAN_FANCTL & (1 << ch)) ? 1 : 0; + return (LM4_FAN_FANCTL & BIT(ch)) ? 1 : 0; } void fan_set_duty(int ch, int percent) diff --git a/chip/lm4/flash.c b/chip/lm4/flash.c index 1c8da9b26a..135b5d0960 100644 --- a/chip/lm4/flash.c +++ b/chip/lm4/flash.c @@ -17,7 +17,7 @@ #define FLASH_FWB_BYTES (FLASH_FWB_WORDS * 4) #define BANK_SHIFT 5 /* bank registers have 32bits each, 2^32 */ -#define BANK_MASK ((1 << BANK_SHIFT) - 1) /* 5 bits */ +#define BANK_MASK (BIT(BANK_SHIFT) - 1) /* 5 bits */ #define F_BANK(b) ((b) >> BANK_SHIFT) #define F_BIT(b) (1 << ((b) & BANK_MASK)) diff --git a/chip/lm4/gpio.c b/chip/lm4/gpio.c index e90eb2bf4f..051e129dbf 100644 --- a/chip/lm4/gpio.c +++ b/chip/lm4/gpio.c @@ -61,7 +61,7 @@ void gpio_set_alternate_function(uint32_t port, uint32_t mask, int func) int i; /* Expand mask from bits to nibbles */ for (i = 0; i < 8; i++) { - if (mask & (1 << i)) + if (mask & BIT(i)) pctlmask |= 1 << (4 * i); } @@ -191,7 +191,7 @@ static int gpio_port_to_clock_gate_mask(uint32_t gpio_port) { int index = find_gpio_port_index(gpio_port); - return index >= 0 ? (1 << index) : 0; + return index >= 0 ? BIT(index) : 0; } #endif diff --git a/chip/lm4/i2c.c b/chip/lm4/i2c.c index 6a746fd9b5..1183ce9550 100644 --- a/chip/lm4/i2c.c +++ b/chip/lm4/i2c.c @@ -201,9 +201,9 @@ int chip_i2c_xfer(int port, int slave_addr, const uint8_t *out, int out_size, i2c_unwedge(port); /* Clock timeout or arbitration lost. Reset port to clear. */ - atomic_or(LM4_SYSTEM_SRI2C_ADDR, (1 << port)); + atomic_or(LM4_SYSTEM_SRI2C_ADDR, BIT(port)); clock_wait_cycles(3); - atomic_clear(LM4_SYSTEM_SRI2C_ADDR, (1 << port)); + atomic_clear(LM4_SYSTEM_SRI2C_ADDR, BIT(port)); clock_wait_cycles(3); /* Restore settings */ diff --git a/chip/lm4/keyboard_raw.c b/chip/lm4/keyboard_raw.c index 85042ce85e..00e00f1c05 100644 --- a/chip/lm4/keyboard_raw.c +++ b/chip/lm4/keyboard_raw.c @@ -68,7 +68,7 @@ test_mockable void keyboard_raw_drive_column(int col) else if (col == KEYBOARD_COLUMN_ALL) mask = 0; /* Assert all outputs */ else - mask = 0x1fff ^ (1 << col); /* Assert a single output */ + mask = 0x1fff ^ BIT(col); /* Assert a single output */ #ifdef CONFIG_KEYBOARD_COL2_INVERTED /* Invert column 2 output */ diff --git a/chip/lm4/lpc.c b/chip/lm4/lpc.c index 745e5e5465..e96e35d359 100644 --- a/chip/lm4/lpc.c +++ b/chip/lm4/lpc.c @@ -747,12 +747,12 @@ static void lpc_init(void) /* Enable LPC channels */ LM4_LPC_LPCCTL = LM4_LPC_SCI_CLK_1 | - (1 << LPC_CH_ACPI) | - (1 << LPC_CH_PORT80) | - (1 << LPC_CH_CMD_DATA) | - (1 << LPC_CH_KEYBOARD) | - (1 << LPC_CH_CMD) | - (1 << LPC_CH_MEMMAP); + BIT(LPC_CH_ACPI) | + BIT(LPC_CH_PORT80) | + BIT(LPC_CH_CMD_DATA) | + BIT(LPC_CH_KEYBOARD) | + BIT(LPC_CH_CMD) | + BIT(LPC_CH_MEMMAP); #ifdef CONFIG_UART_HOST LM4_LPC_LPCCTL |= 1 << LPC_CH_COMX; diff --git a/chip/lm4/uart.c b/chip/lm4/uart.c index 6ef9f67834..04a22c382c 100644 --- a/chip/lm4/uart.c +++ b/chip/lm4/uart.c @@ -193,7 +193,7 @@ void uart_init(void) clock_enable_peripheral(CGC_OFFSET_UART, mask, CGC_MODE_ALL); #ifdef CONFIG_UART_HOST - mask |= (1 << CONFIG_UART_HOST); + mask |= BIT(CONFIG_UART_HOST); #endif clock_enable_peripheral(CGC_OFFSET_UART, mask, diff --git a/chip/mchp/gpio.c b/chip/mchp/gpio.c index aa95b8fb0d..eed5c3efbc 100644 --- a/chip/mchp/gpio.c +++ b/chip/mchp/gpio.c @@ -62,7 +62,7 @@ void gpio_set_alternate_function(uint32_t port, uint32_t mask, int func) if (func > 0) val |= (func & 0x3) << 12; MCHP_GPIO_CTL(port, i) = val; - mask &= ~(1 << i); + mask &= ~BIT(i); } } @@ -111,7 +111,7 @@ void gpio_set_flags_by_mask(uint32_t port, uint32_t mask, uint32_t flags) while (mask) { i = GPIO_MASK_TO_NUM(mask); - mask &= ~(1 << i); + mask &= ~BIT(i); val = MCHP_GPIO_CTL(port, i); #ifdef CONFIG_GPIO_POWER_DOWN @@ -191,7 +191,7 @@ void gpio_power_off_by_mask(uint32_t port, uint32_t mask) while (mask) { i = GPIO_MASK_TO_NUM(mask); - mask &= ~(1 << i); + mask &= ~BIT(i); MCHP_GPIO_CTL(port, i) = (MCHP_GPIO_CTRL_PWR_OFF + MCHP_GPIO_INTDET_DISABLED); @@ -235,8 +235,8 @@ int gpio_enable_interrupt(enum gpio_signal signal) port = gpio_list[signal].port; girq_id = int_map[port].girq_id; - MCHP_INT_ENABLE(girq_id) = (1 << i); - MCHP_INT_BLK_EN |= (1 << girq_id); + MCHP_INT_ENABLE(girq_id) = BIT(i); + MCHP_INT_BLK_EN |= BIT(girq_id); return EC_SUCCESS; } @@ -253,7 +253,7 @@ int gpio_disable_interrupt(enum gpio_signal signal) girq_id = int_map[port].girq_id; - MCHP_INT_DISABLE(girq_id) = (1 << i); + MCHP_INT_DISABLE(girq_id) = BIT(i); return EC_SUCCESS; } @@ -291,7 +291,7 @@ int gpio_clear_pending_interrupt(enum gpio_signal signal) girq_id = int_map[port].girq_id; /* Clear interrupt source sticky status bit even if not enabled */ - MCHP_INT_SOURCE(girq_id) = (1 << i); + MCHP_INT_SOURCE(girq_id) = BIT(i); i = MCHP_INT_SOURCE(girq_id); task_clear_pending_irq(girq_id - 8); @@ -394,13 +394,13 @@ static void gpio_interrupt(int girq, int port) bit = __builtin_ffs(g->mask); if (bit) { bit--; - if (sts & (1 << bit)) { + if (sts & BIT(bit)) { trace12(0, GPIO, 0, "Bit[%d]: handler @ 0x%08x", bit, (uint32_t)gpio_irq_handlers[i]); gpio_irq_handlers[i](i); } - sts &= ~(1 << bit); + sts &= ~BIT(bit); } } } diff --git a/chip/mchp/hwtimer.c b/chip/mchp/hwtimer.c index a69fa4ab7e..e84f278f4a 100644 --- a/chip/mchp/hwtimer.c +++ b/chip/mchp/hwtimer.c @@ -115,7 +115,7 @@ int __hw_clock_source_init(uint32_t start_t) MCHP_TMR32_GIRQ_BIT(1); /* * Not needed when using direct mode interrupts - * MCHP_INT_BLK_EN |= (1 << MCHP_TMR32_GIRQ); + * MCHP_INT_BLK_EN |= BIT(MCHP_TMR32_GIRQ); */ return MCHP_IRQ_TIMER32_1; } diff --git a/chip/mec1322/gpio.c b/chip/mec1322/gpio.c index c3b62ad583..4e532e75d0 100644 --- a/chip/mec1322/gpio.c +++ b/chip/mec1322/gpio.c @@ -42,7 +42,7 @@ void gpio_set_alternate_function(uint32_t port, uint32_t mask, int func) if (func > 0) val |= (func & 0x3) << 12; MEC1322_GPIO_CTL(port, i) = val; - mask &= ~(1 << i); + mask &= ~BIT(i); } } @@ -81,7 +81,7 @@ void gpio_set_flags_by_mask(uint32_t port, uint32_t mask, uint32_t flags) uint32_t val; while (mask) { i = GPIO_MASK_TO_NUM(mask); - mask &= ~(1 << i); + mask &= ~BIT(i); val = MEC1322_GPIO_CTL(port, i); /* @@ -150,8 +150,8 @@ int gpio_enable_interrupt(enum gpio_signal signal) girq_id = int_map[port].girq_id; bit_id = (port - int_map[port].port_offset) * 8 + i; - MEC1322_INT_ENABLE(girq_id) |= (1 << bit_id); - MEC1322_INT_BLK_EN |= (1 << girq_id); + MEC1322_INT_ENABLE(girq_id) |= BIT(bit_id); + MEC1322_INT_BLK_EN |= BIT(girq_id); return EC_SUCCESS; } @@ -168,7 +168,7 @@ int gpio_disable_interrupt(enum gpio_signal signal) girq_id = int_map[port].girq_id; bit_id = (port - int_map[port].port_offset) * 8 + i; - MEC1322_INT_DISABLE(girq_id) = (1 << bit_id); + MEC1322_INT_DISABLE(girq_id) = BIT(bit_id); return EC_SUCCESS; } @@ -258,9 +258,9 @@ static void gpio_interrupt(int girq, int port_offset) for (i = 0; i < GPIO_IH_COUNT && sts; ++i, ++g) { bit = (g->port - port_offset) * 8 + __builtin_ffs(g->mask) - 1; - if (sts & (1 << bit)) + if (sts & BIT(bit)) gpio_irq_handlers[i](i); - sts &= ~(1 << bit); + sts &= ~BIT(bit); } } diff --git a/chip/mec1322/i2c.c b/chip/mec1322/i2c.c index 2c22256d81..8c59be9a38 100644 --- a/chip/mec1322/i2c.c +++ b/chip/mec1322/i2c.c @@ -120,7 +120,7 @@ static void configure_controller(int controller, int kbps) /* Enable interrupt */ MEC1322_I2C_CONFIG(controller) |= BIT(29); /* ENIDI */ - MEC1322_INT_ENABLE(12) |= (1 << controller); + MEC1322_INT_ENABLE(12) |= BIT(controller); MEC1322_INT_BLK_EN |= BIT(12); } diff --git a/chip/mt_scp/gpio.c b/chip/mt_scp/gpio.c index 7d680e6863..896baab93a 100644 --- a/chip/mt_scp/gpio.c +++ b/chip/mt_scp/gpio.c @@ -162,9 +162,9 @@ void __keep gpio_interrupt(void) while (pending) { bit = get_next_bit(&pending); - SCP_EINT_ACK[port] = (1 << bit); + SCP_EINT_ACK[port] = BIT(bit); /* Skip masked gpio */ - if (SCP_EINT_MASK_GET[port] & (1 << bit)) + if (SCP_EINT_MASK_GET[port] & BIT(bit)) continue; /* Call handler */ signal = port * 32 + bit; diff --git a/chip/mt_scp/registers.h b/chip/mt_scp/registers.h index 07634562a9..e6bcbecac3 100644 --- a/chip/mt_scp/registers.h +++ b/chip/mt_scp/registers.h @@ -155,7 +155,7 @@ #define SCP_REMAP_CFG3 REG32(SCP_CFG_BASE + 0x128) #define SCP_REMAP_ADDR_SHIFT 28 -#define SCP_REMAP_ADDR_LSB_MASK ((1 << SCP_REMAP_ADDR_SHIFT) - 1) +#define SCP_REMAP_ADDR_LSB_MASK (BIT(SCP_REMAP_ADDR_SHIFT) - 1) #define SCP_REMAP_ADDR_MSB_MASK ((~0) << SCP_REMAP_ADDR_SHIFT) /* Cached memory remap control */ @@ -184,7 +184,7 @@ #define SCP_L1_EXT_ADDR_SHIFT 20 #define SCP_L1_EXT_ADDR_OTHER_SHIFT 28 -#define SCP_L1_EXT_ADDR_OTHER_LSB_MASK ((1 << SCP_REMAP_ADDR_SHIFT) - 1) +#define SCP_L1_EXT_ADDR_OTHER_LSB_MASK (BIT(SCP_REMAP_ADDR_SHIFT) - 1) #define SCP_L1_EXT_ADDR_OTHER_MSB_MASK ((~0) << SCP_REMAP_ADDR_SHIFT) /* INTC control */ @@ -426,7 +426,7 @@ #define SCP_CACHE_OP_TADDR_SHIFT 5 #define SCP_CACHE_OP_TADDR_MASK (0x7ffffff << SCP_CACHE_OP_TADDR_SHIFT) -#define SCP_CACHE_LINE_SIZE (1 << SCP_CACHE_OP_TADDR_SHIFT) +#define SCP_CACHE_LINE_SIZE BIT(SCP_CACHE_OP_TADDR_SHIFT) /* Cache statistics */ #define SCP_CACHE_HCNT0L(x) REG32(SCP_CACHE_SEL(x) + 0x08) diff --git a/chip/mt_scp/uart.c b/chip/mt_scp/uart.c index 94f78748dd..8717d74704 100644 --- a/chip/mt_scp/uart.c +++ b/chip/mt_scp/uart.c @@ -109,7 +109,7 @@ void uart_rx_interrupt(void) uint8_t ier; task_clear_pending_irq(UART_RX_IRQ(UARTN)); - SCP_INTC_UART_RX_IRQ &= ~(1 << UARTN); + SCP_INTC_UART_RX_IRQ &= ~BIT(UARTN); uart_process(); ier = UART_IER(UARTN); UART_IER(UARTN) = 0; diff --git a/chip/npcx/cec.c b/chip/npcx/cec.c index d996695dfc..8c544c5970 100644 --- a/chip/npcx/cec.c +++ b/chip/npcx/cec.c @@ -791,7 +791,7 @@ void cec_isr(void) /* Retrieve events NPCX_TECTRL_TAXND */ events = GET_FIELD(NPCX_TECTRL(mdl), FIELD(0, 4)); - if (events & (1 << NPCX_TECTRL_TAPND)) { + if (events & BIT(NPCX_TECTRL_TAPND)) { /* Capture event */ cec_event_cap(); } else { @@ -801,11 +801,11 @@ void cec_isr(void) * happening, since we will get both events in the * edge-trigger case */ - if (events & (1 << NPCX_TECTRL_TCPND)) + if (events & BIT(NPCX_TECTRL_TCPND)) cec_event_timeout(); } /* Oneshot timer, a transfer has been initiated from AP */ - if (events & (1 << NPCX_TECTRL_TDPND)) { + if (events & BIT(NPCX_TECTRL_TDPND)) { tmr2_stop(); cec_event_tx(); } diff --git a/chip/npcx/config_chip.h b/chip/npcx/config_chip.h index 97f52963fd..7512e5a399 100644 --- a/chip/npcx/config_chip.h +++ b/chip/npcx/config_chip.h @@ -66,7 +66,7 @@ /* Default use UART1 as console */ #define CONFIG_CONSOLE_UART 0 -#define GPIO_PIN(port, index) GPIO_##port, (1 << index) +#define GPIO_PIN(port, index) GPIO_##port, BIT(index) #define GPIO_PIN_MASK(p, m) .port = GPIO_##p, .mask = (m) #endif /* __CROS_EC_CONFIG_CHIP_H */ diff --git a/chip/npcx/espi.c b/chip/npcx/espi.c index 21766701a0..d092327aed 100644 --- a/chip/npcx/espi.c +++ b/chip/npcx/espi.c @@ -532,7 +532,7 @@ void espi_interrupt(void) * Bit 17 of ESPIIE is reserved. We need to set the same bit in mask * in case bit 17 in ESPISTS of npcx7 is not cleared in ISR. */ - mask = NPCX_ESPIIE | (1 << NPCX_ESPISTS_VWUPDW); + mask = NPCX_ESPIIE | BIT(NPCX_ESPISTS_VWUPDW); #else mask = NPCX_ESPIIE; #endif diff --git a/chip/npcx/gpio.c b/chip/npcx/gpio.c index 252b915e45..8a76043d3d 100644 --- a/chip/npcx/gpio.c +++ b/chip/npcx/gpio.c @@ -313,7 +313,7 @@ void gpio_set_alternate_function(uint32_t port, uint32_t mask, int func) /* check each bit from mask */ for (pin = 0; pin < 8; pin++) - if (mask & (1 << pin)) + if (mask & BIT(pin)) gpio_alt_sel(port, pin, func); } diff --git a/chip/npcx/hwtimer.c b/chip/npcx/hwtimer.c index 76f1822a94..a201a75219 100644 --- a/chip/npcx/hwtimer.c +++ b/chip/npcx/hwtimer.c @@ -20,7 +20,7 @@ /* Depth of event timer */ #define TICK_EVT_DEPTH 16 /* Depth of event timer Unit: bits */ -#define TICK_EVT_INTERVAL (1 << TICK_EVT_DEPTH) /* Unit: us */ +#define TICK_EVT_INTERVAL BIT(TICK_EVT_DEPTH) /* Unit: us */ #define TICK_EVT_INTERVAL_MASK (TICK_EVT_INTERVAL - 1) /* Mask of interval */ #define TICK_EVT_MAX_CNT (TICK_EVT_INTERVAL - 1) /* Maximum event counter */ diff --git a/chip/npcx/keyboard_raw.c b/chip/npcx/keyboard_raw.c index 97a563c53f..9ed18b3739 100644 --- a/chip/npcx/keyboard_raw.c +++ b/chip/npcx/keyboard_raw.c @@ -101,7 +101,7 @@ test_mockable void keyboard_raw_drive_column(int col) } /* Set KBSOUT to zero to detect key-press */ else if (col == KEYBOARD_COLUMN_ALL) { - mask = ~((1 << keyboard_cols) - 1); + mask = ~(BIT(keyboard_cols) - 1); #ifdef CONFIG_KEYBOARD_COL2_INVERTED gpio_set_level(GPIO_KBD_KSO2, 1); #endif @@ -114,7 +114,7 @@ test_mockable void keyboard_raw_drive_column(int col) else gpio_set_level(GPIO_KBD_KSO2, 0); #endif - mask = ~(1 << col_out); + mask = ~BIT(col_out); } /* Set KBSOUT */ @@ -158,6 +158,6 @@ DECLARE_IRQ(NPCX_IRQ_KSI_WKINTC_1, keyboard_raw_interrupt, 5); int keyboard_raw_is_input_low(int port, int id) { - return (NPCX_PDIN(port) & (1 << id)) == 0; + return (NPCX_PDIN(port) & BIT(id)) == 0; } diff --git a/chip/npcx/lpc.c b/chip/npcx/lpc.c index 971512ec72..74d7f29d99 100644 --- a/chip/npcx/lpc.c +++ b/chip/npcx/lpc.c @@ -981,7 +981,7 @@ static void lpc_init(void) CLEAR_BIT(NPCX_HIPMIC(PMC_ACPI), NPCX_HIPMIC_SMIPOL); /* Set SMIB/SCIB to make sure SMI/SCI are high at init */ NPCX_HIPMIC(PMC_ACPI) = NPCX_HIPMIC(PMC_ACPI) - | (1 << NPCX_HIPMIC_SMIB) | (1 << NPCX_HIPMIC_SCIB); + | BIT(NPCX_HIPMIC_SMIB) | BIT(NPCX_HIPMIC_SCIB); #ifndef CONFIG_SCI_GPIO /* * Allow SMI/SCI generated from PM module. diff --git a/chip/npcx/registers.h b/chip/npcx/registers.h index 7c812e5da2..c13395eaa4 100644 --- a/chip/npcx/registers.h +++ b/chip/npcx/registers.h @@ -1005,44 +1005,44 @@ enum NPCX_PMC_PWDWN_CTL_T { }; /* TODO: set PD masks based upon actual peripheral usage */ -#define CGC_KBS_MASK (1 << NPCX_PWDWN_CTL1_KBS_PD) -#define CGC_UART_MASK (1 << NPCX_PWDWN_CTL1_UART_PD) -#define CGC_FAN_MASK ((1 << NPCX_PWDWN_CTL1_MFT1_PD) | \ - (1 << NPCX_PWDWN_CTL1_MFT2_PD)) -#define CGC_FIU_MASK (1 << NPCX_PWDWN_CTL1_FIU_PD) +#define CGC_KBS_MASK BIT(NPCX_PWDWN_CTL1_KBS_PD) +#define CGC_UART_MASK BIT(NPCX_PWDWN_CTL1_UART_PD) +#define CGC_FAN_MASK (BIT(NPCX_PWDWN_CTL1_MFT1_PD) | \ + BIT(NPCX_PWDWN_CTL1_MFT2_PD)) +#define CGC_FIU_MASK BIT(NPCX_PWDWN_CTL1_FIU_PD) #if defined(CHIP_FAMILY_NPCX5) -#define CGC_I2C_MASK ((1 << NPCX_PWDWN_CTL3_SMB0_PD) | \ - (1 << NPCX_PWDWN_CTL3_SMB1_PD) | \ - (1 << NPCX_PWDWN_CTL3_SMB2_PD) | \ - (1 << NPCX_PWDWN_CTL3_SMB3_PD)) +#define CGC_I2C_MASK (BIT(NPCX_PWDWN_CTL3_SMB0_PD) | \ + BIT(NPCX_PWDWN_CTL3_SMB1_PD) | \ + BIT(NPCX_PWDWN_CTL3_SMB2_PD) | \ + BIT(NPCX_PWDWN_CTL3_SMB3_PD)) #elif defined(CHIP_FAMILY_NPCX7) -#define CGC_I2C_MASK ((1 << NPCX_PWDWN_CTL3_SMB0_PD) | \ - (1 << NPCX_PWDWN_CTL3_SMB1_PD) | \ - (1 << NPCX_PWDWN_CTL3_SMB2_PD) | \ - (1 << NPCX_PWDWN_CTL3_SMB3_PD) | \ - (1 << NPCX_PWDWN_CTL3_SMB4_PD)) -#define CGC_I2C_MASK2 ((1 << NPCX_PWDWN_CTL7_SMB5_PD) | \ - (1 << NPCX_PWDWN_CTL7_SMB6_PD) | \ - (1 << NPCX_PWDWN_CTL7_SMB7_PD)) +#define CGC_I2C_MASK (BIT(NPCX_PWDWN_CTL3_SMB0_PD) | \ + BIT(NPCX_PWDWN_CTL3_SMB1_PD) | \ + BIT(NPCX_PWDWN_CTL3_SMB2_PD) | \ + BIT(NPCX_PWDWN_CTL3_SMB3_PD) | \ + BIT(NPCX_PWDWN_CTL3_SMB4_PD)) +#define CGC_I2C_MASK2 (BIT(NPCX_PWDWN_CTL7_SMB5_PD) | \ + BIT(NPCX_PWDWN_CTL7_SMB6_PD) | \ + BIT(NPCX_PWDWN_CTL7_SMB7_PD)) #ifdef NPCX_SECOND_UART -#define CGC_UART2_MASK (1 << NPCX_PWDWN_CTL7_UART2_PD) +#define CGC_UART2_MASK BIT(NPCX_PWDWN_CTL7_UART2_PD) #endif #ifdef NPCX_WOV_SUPPORT -#define CGC_WOV_MASK (1 << NPCX_PWDWN_CTL7_WOV_PD) +#define CGC_WOV_MASK BIT(NPCX_PWDWN_CTL7_WOV_PD) #endif #endif -#define CGC_ADC_MASK (1 << NPCX_PWDWN_CTL4_ADC_PD) -#define CGC_PECI_MASK (1 << NPCX_PWDWN_CTL4_PECI_PD) -#define CGC_SPI_MASK (1 << NPCX_PWDWN_CTL4_SPIP_PD) -#define CGC_TIMER_MASK ((1 << NPCX_PWDWN_CTL4_ITIM1_PD) | \ - (1 << NPCX_PWDWN_CTL4_ITIM2_PD) | \ - (1 << NPCX_PWDWN_CTL4_ITIM3_PD)) -#define CGC_LPC_MASK ((1 << NPCX_PWDWN_CTL5_C2HACC_PD) | \ - (1 << NPCX_PWDWN_CTL5_SHM_REG_PD) | \ - (1 << NPCX_PWDWN_CTL5_SHM_PD) | \ - (1 << NPCX_PWDWN_CTL5_DP80_PD) | \ - (1 << NPCX_PWDWN_CTL5_MSWC_PD)) -#define CGC_ESPI_MASK (1 << NPCX_PWDWN_CTL6_ESPI_PD) +#define CGC_ADC_MASK BIT(NPCX_PWDWN_CTL4_ADC_PD) +#define CGC_PECI_MASK BIT(NPCX_PWDWN_CTL4_PECI_PD) +#define CGC_SPI_MASK BIT(NPCX_PWDWN_CTL4_SPIP_PD) +#define CGC_TIMER_MASK (BIT(NPCX_PWDWN_CTL4_ITIM1_PD) | \ + BIT(NPCX_PWDWN_CTL4_ITIM2_PD) | \ + BIT(NPCX_PWDWN_CTL4_ITIM3_PD)) +#define CGC_LPC_MASK (BIT(NPCX_PWDWN_CTL5_C2HACC_PD) | \ + BIT(NPCX_PWDWN_CTL5_SHM_REG_PD) | \ + BIT(NPCX_PWDWN_CTL5_SHM_PD) | \ + BIT(NPCX_PWDWN_CTL5_DP80_PD) | \ + BIT(NPCX_PWDWN_CTL5_MSWC_PD)) +#define CGC_ESPI_MASK BIT(NPCX_PWDWN_CTL6_ESPI_PD) /******************************************************************************/ /* Flash Interface Unit (FIU) Registers */ @@ -1242,11 +1242,11 @@ enum PM_CHANNEL_T { #define NPCX_BKUP_STS_VSBY_STS 1 #define NPCX_BKUP_STS_VCC1_STS 0 #define NPCX_BKUP_STS_ALL_MASK \ - ((1 << NPCX_BKUP_STS_IBBR) | (1 << NPCX_BKUP_STS_VSBY_STS) | \ - (1 << NPCX_BKUP_STS_VCC1_STS)) + (BIT(NPCX_BKUP_STS_IBBR) | BIT(NPCX_BKUP_STS_VSBY_STS) | \ + BIT(NPCX_BKUP_STS_VCC1_STS)) #define NPCX_BBRAM_SIZE 128 /* Size of BBRAM */ #else -#define NPCX_BKUP_STS_ALL_MASK (1 << NPCX_BKUP_STS_IBBR) +#define NPCX_BKUP_STS_ALL_MASK BIT(NPCX_BKUP_STS_IBBR) #define NPCX_BBRAM_SIZE 64 /* Size of BBRAM */ #endif @@ -1625,32 +1625,32 @@ enum ITIM16_MODULE_T { #define ENABLE_ESPI_CHAN(ch) SET_BIT(NPCX_ESPICFG, ch) #define DISABLE_ESPI_CHAN(ch) CLEAR_BIT(NPCX_ESPICFG, ch) /* ESPI Slave Channel Support Definitions */ -#define ESPI_SUPP_CH_PC (1 << NPCX_ESPICFG_PCCHN_SUPP) -#define ESPI_SUPP_CH_VM (1 << NPCX_ESPICFG_VWCHN_SUPP) -#define ESPI_SUPP_CH_OOB (1 << NPCX_ESPICFG_OOBCHN_SUPP) -#define ESPI_SUPP_CH_FLASH (1 << NPCX_ESPICFG_FLASHCHN_SUPP) +#define ESPI_SUPP_CH_PC BIT(NPCX_ESPICFG_PCCHN_SUPP) +#define ESPI_SUPP_CH_VM BIT(NPCX_ESPICFG_VWCHN_SUPP) +#define ESPI_SUPP_CH_OOB BIT(NPCX_ESPICFG_OOBCHN_SUPP) +#define ESPI_SUPP_CH_FLASH BIT(NPCX_ESPICFG_FLASHCHN_SUPP) #define ESPI_SUPP_CH_ALL (ESPI_SUPP_CH_PC | ESPI_SUPP_CH_VM | \ ESPI_SUPP_CH_OOB | ESPI_SUPP_CH_FLASH) /* ESPI Interrupts Enable Definitions */ -#define ESPIIE_IBRST (1 << NPCX_ESPIIE_IBRSTIE) -#define ESPIIE_CFGUPD (1 << NPCX_ESPIIE_CFGUPDIE) -#define ESPIIE_BERR (1 << NPCX_ESPIIE_BERRIE) -#define ESPIIE_OOBRX (1 << NPCX_ESPIIE_OOBRXIE) -#define ESPIIE_FLASHRX (1 << NPCX_ESPIIE_FLASHRXIE) -#define ESPIIE_SFLASHRD (1 << NPCX_ESPIIE_SFLASHRDIE) -#define ESPIIE_PERACC (1 << NPCX_ESPIIE_PERACCIE) -#define ESPIIE_DFRD (1 << NPCX_ESPIIE_DFRDIE) -#define ESPIIE_VWUPD (1 << NPCX_ESPIIE_VWUPDIE) -#define ESPIIE_ESPIRST (1 << NPCX_ESPIIE_ESPIRSTIE) -#define ESPIIE_PLTRST (1 << NPCX_ESPIIE_PLTRSTIE) -#define ESPIIE_AMERR (1 << NPCX_ESPIIE_AMERRIE) -#define ESPIIE_AMDONE (1 << NPCX_ESPIIE_AMDONEIE) +#define ESPIIE_IBRST BIT(NPCX_ESPIIE_IBRSTIE) +#define ESPIIE_CFGUPD BIT(NPCX_ESPIIE_CFGUPDIE) +#define ESPIIE_BERR BIT(NPCX_ESPIIE_BERRIE) +#define ESPIIE_OOBRX BIT(NPCX_ESPIIE_OOBRXIE) +#define ESPIIE_FLASHRX BIT(NPCX_ESPIIE_FLASHRXIE) +#define ESPIIE_SFLASHRD BIT(NPCX_ESPIIE_SFLASHRDIE) +#define ESPIIE_PERACC BIT(NPCX_ESPIIE_PERACCIE) +#define ESPIIE_DFRD BIT(NPCX_ESPIIE_DFRDIE) +#define ESPIIE_VWUPD BIT(NPCX_ESPIIE_VWUPDIE) +#define ESPIIE_ESPIRST BIT(NPCX_ESPIIE_ESPIRSTIE) +#define ESPIIE_PLTRST BIT(NPCX_ESPIIE_PLTRSTIE) +#define ESPIIE_AMERR BIT(NPCX_ESPIIE_AMERRIE) +#define ESPIIE_AMDONE BIT(NPCX_ESPIIE_AMDONEIE) #if defined(CHIP_FAMILY_NPCX7) -#define ESPIIE_BMTXDONE (1 << NPCX_ESPIIE_BMTXDONEIE) -#define ESPIIE_PBMRX (1 << NPCX_ESPIIE_PBMRXIE) -#define ESPIIE_PMSGRX (1 << NPCX_ESPIIE_PMSGRXIE) -#define ESPIIE_BMBURSTERR (1 << NPCX_ESPIIE_BMBURSTERRIE) -#define ESPIIE_BMBURSTDONE (1 << NPCX_ESPIIE_BMBURSTDONEIE) +#define ESPIIE_BMTXDONE BIT(NPCX_ESPIIE_BMTXDONEIE) +#define ESPIIE_PBMRX BIT(NPCX_ESPIIE_PBMRXIE) +#define ESPIIE_PMSGRX BIT(NPCX_ESPIIE_PMSGRXIE) +#define ESPIIE_BMBURSTERR BIT(NPCX_ESPIIE_BMBURSTERRIE) +#define ESPIIE_BMBURSTDONE BIT(NPCX_ESPIIE_BMBURSTDONEIE) #endif /* eSPI Interrupts for VW */ #define ESPIIE_VW (ESPIIE_VWUPD | ESPIIE_PLTRST) @@ -1658,18 +1658,18 @@ enum ITIM16_MODULE_T { #define ESPIIE_GENERIC (ESPIIE_IBRST | ESPIIE_CFGUPD | \ ESPIIE_BERR | ESPIIE_ESPIRST) /* ESPI Wake-up Enable Definitions */ -#define ESPIWE_IBRST (1 << NPCX_ESPIWE_IBRSTWE) -#define ESPIWE_CFGUPD (1 << NPCX_ESPIWE_CFGUPDWE) -#define ESPIWE_BERR (1 << NPCX_ESPIWE_BERRWE) -#define ESPIWE_OOBRX (1 << NPCX_ESPIWE_OOBRXWE) -#define ESPIWE_FLASHRX (1 << NPCX_ESPIWE_FLASHRXWE) -#define ESPIWE_PERACC (1 << NPCX_ESPIWE_PERACCWE) -#define ESPIWE_DFRD (1 << NPCX_ESPIWE_DFRDWE) -#define ESPIWE_VWUPD (1 << NPCX_ESPIWE_VWUPDWE) -#define ESPIWE_ESPIRST (1 << NPCX_ESPIWE_ESPIRSTWE) +#define ESPIWE_IBRST BIT(NPCX_ESPIWE_IBRSTWE) +#define ESPIWE_CFGUPD BIT(NPCX_ESPIWE_CFGUPDWE) +#define ESPIWE_BERR BIT(NPCX_ESPIWE_BERRWE) +#define ESPIWE_OOBRX BIT(NPCX_ESPIWE_OOBRXWE) +#define ESPIWE_FLASHRX BIT(NPCX_ESPIWE_FLASHRXWE) +#define ESPIWE_PERACC BIT(NPCX_ESPIWE_PERACCWE) +#define ESPIWE_DFRD BIT(NPCX_ESPIWE_DFRDWE) +#define ESPIWE_VWUPD BIT(NPCX_ESPIWE_VWUPDWE) +#define ESPIWE_ESPIRST BIT(NPCX_ESPIWE_ESPIRSTWE) #if defined(CHIP_FAMILY_NPCX7) -#define ESPIWE_PBMRX (1 << NPCX_ESPIWE_PBMRXWE) -#define ESPIWE_PMSGRX (1 << NPCX_ESPIWE_PMSGRXWE) +#define ESPIWE_PBMRX BIT(NPCX_ESPIWE_PBMRXWE) +#define ESPIWE_PMSGRX BIT(NPCX_ESPIWE_PMSGRXWE) #endif /* eSPI Wake-up enable for VW */ #define ESPIWE_VW ESPIWE_VWUPD diff --git a/chip/npcx/shi.c b/chip/npcx/shi.c index 2e061ad2c2..2f084c597e 100644 --- a/chip/npcx/shi.c +++ b/chip/npcx/shi.c @@ -661,7 +661,7 @@ void shi_int_handler(void) /* SHI CS pin is asserted in EVSTAT2 */ if (IS_BIT_SET(stat2_reg, NPCX_EVSTAT2_CSNFE)) { /* clear CSNFE bit */ - NPCX_EVSTAT2 = (1 << NPCX_EVSTAT2_CSNFE); + NPCX_EVSTAT2 = BIT(NPCX_EVSTAT2_CSNFE); DEBUG_CPRINTF("CSNFE-"); /* * BUSY bit is set when SHI_CS is asserted. If not, leave it for @@ -688,7 +688,7 @@ void shi_int_handler(void) */ if (IS_BIT_SET(stat2_reg, NPCX_EVSTAT2_CSNRE)) { /* Clear pending bit of CSNRE */ - NPCX_EVSTAT2 = (1 << NPCX_EVSTAT2_CSNRE); + NPCX_EVSTAT2 = BIT(NPCX_EVSTAT2_CSNRE); #else if (IS_BIT_SET(stat_reg, NPCX_EVSTAT_EOR)) { #endif @@ -784,7 +784,7 @@ void shi_int_handler(void) */ if (IS_BIT_SET(stat2_reg, NPCX_EVSTAT2_IBHF2)) { /* Clear IBHF2 */ - NPCX_EVSTAT2 = (1 << NPCX_EVSTAT2_IBHF2); + NPCX_EVSTAT2 = BIT(NPCX_EVSTAT2_IBHF2); DEBUG_CPRINTF("HDR-"); /* Disable second IBF interrupt and start to parse header */ shi_sec_ibf_int_enable(0); diff --git a/chip/npcx/system-npcx7.c b/chip/npcx/system-npcx7.c index 579b2a1321..6b0e5157ea 100644 --- a/chip/npcx/system-npcx7.c +++ b/chip/npcx/system-npcx7.c @@ -22,7 +22,7 @@ /* Macros for last 32K ram block */ #define LAST_RAM_BLK ((NPCX_RAM_SIZE / (32 * 1024)) - 1) -#define RAM_PD_MASK (~(1 << LAST_RAM_BLK)) +#define RAM_PD_MASK (BIT(LAST_RAM_BLK) - 1) /*****************************************************************************/ /* IC specific low-level driver depends on chip series */ diff --git a/chip/npcx/system.c b/chip/npcx/system.c index b9d3367d91..4b2f55ddb4 100644 --- a/chip/npcx/system.c +++ b/chip/npcx/system.c @@ -117,7 +117,7 @@ static int bbram_valid(enum bbram_data_index index, int bytes) /* Check BBRAM is valid */ if (IS_BIT_SET(NPCX_BKUP_STS, NPCX_BKUP_STS_IBBR)) { - NPCX_BKUP_STS = (1 << NPCX_BKUP_STS_IBBR); + NPCX_BKUP_STS = BIT(NPCX_BKUP_STS_IBBR); panic_printf("IBBR set: BBRAM corrupted!\n"); return 0; } @@ -693,8 +693,8 @@ void system_pre_init(void) NPCX_PWDWN_CTL(NPCX_PMC_PWDWN_5) = 0xF8; pwdwn6 = 0x70 | - (1 << NPCX_PWDWN_CTL6_ITIM6_PD) | - (1 << NPCX_PWDWN_CTL6_ITIM4_PD); /* Skip ITIM5_PD */ + BIT(NPCX_PWDWN_CTL6_ITIM6_PD) | + BIT(NPCX_PWDWN_CTL6_ITIM4_PD); /* Skip ITIM5_PD */ #if !defined(CONFIG_HOSTCMD_ESPI) pwdwn6 |= 1 << NPCX_PWDWN_CTL6_ESPI_PD; #endif diff --git a/chip/npcx/uartn.c b/chip/npcx/uartn.c index d7d46e849f..692e75419f 100644 --- a/chip/npcx/uartn.c +++ b/chip/npcx/uartn.c @@ -188,9 +188,9 @@ static void uartn_set_fifo_mode(uint8_t uart_num) /* Enable the UART FIFO mode */ SET_BIT(NPCX_UMDSL(uart_num), NPCX_UMDSL_FIFO_MD); /* Disable all Tx interrupts */ - NPCX_UFTCTL(uart_num) &= ~((1 << NPCX_UFTCTL_TEMPTY_LVL_EN) | - (1 << NPCX_UFTCTL_TEMPTY_EN) | - (1 << NPCX_UFTCTL_NXIMPEN)); + NPCX_UFTCTL(uart_num) &= ~(BIT(NPCX_UFTCTL_TEMPTY_LVL_EN) | + BIT(NPCX_UFTCTL_TEMPTY_EN) | + BIT(NPCX_UFTCTL_NXIMPEN)); } #endif diff --git a/chip/nrf51/bluetooth_le.c b/chip/nrf51/bluetooth_le.c index 7fe80ff8e1..f4747cf83e 100644 --- a/chip/nrf51/bluetooth_le.c +++ b/chip/nrf51/bluetooth_le.c @@ -48,20 +48,20 @@ static void nrf2ble_packet(struct ble_pdu *ble_p, ble_p->header_type_adv = 1; ble_p->header.adv.type = radio_p->s0 & 0xf; ble_p->header.adv.txaddr = (radio_p->s0 & - (1 << BLE_ADV_HEADER_TXADD_SHIFT)) != 0; + BIT(BLE_ADV_HEADER_TXADD_SHIFT)) != 0; ble_p->header.adv.rxaddr = (radio_p->s0 & - (1 << BLE_ADV_HEADER_RXADD_SHIFT)) != 0; + BIT(BLE_ADV_HEADER_RXADD_SHIFT)) != 0; /* Length check? 6-37 Bytes */ ble_p->header.adv.length = radio_p->length; } else { ble_p->header_type_adv = 0; ble_p->header.data.llid = radio_p->s0 & 0x3; ble_p->header.data.nesn = (radio_p->s0 & - (1 << BLE_DATA_HEADER_NESN_SHIFT)) != 0; + BIT(BLE_DATA_HEADER_NESN_SHIFT)) != 0; ble_p->header.data.sn = (radio_p->s0 & - (1 << BLE_DATA_HEADER_SN_SHIFT)) != 0; + BIT(BLE_DATA_HEADER_SN_SHIFT)) != 0; ble_p->header.data.md = (radio_p->s0 & - (1 << BLE_DATA_HEADER_MD_SHIFT)) != 0; + BIT(BLE_DATA_HEADER_MD_SHIFT)) != 0; /* Length check? 0-31 Bytes */ ble_p->header.data.length = radio_p->length; } @@ -170,8 +170,8 @@ int ble_rx(struct ble_pdu *pdu, int timeout, int adv) */ ppi_channel_requested = NRF51_PPI_CH_RADIO_ADDR__TIMER0CC1; if (ppi_request_channel(&ppi_channel_requested) == EC_SUCCESS) { - NRF51_PPI_CHEN |= (1 << ppi_channel_requested); - NRF51_PPI_CHENSET |= (1 << ppi_channel_requested); + NRF51_PPI_CHEN |= BIT(ppi_channel_requested); + NRF51_PPI_CHENSET |= BIT(ppi_channel_requested); } diff --git a/chip/nrf51/config_chip.h b/chip/nrf51/config_chip.h index 374101d1bb..eb2ee93509 100644 --- a/chip/nrf51/config_chip.h +++ b/chip/nrf51/config_chip.h @@ -57,7 +57,7 @@ #undef CONFIG_UART_TX_BUF_SIZE #define CONFIG_UART_TX_BUF_SIZE 1024 -#define GPIO_PIN(port, index) GPIO_##port, (1 << index) +#define GPIO_PIN(port, index) GPIO_##port, BIT(index) #define GPIO_PIN_MASK(p, m) .port = GPIO_##p, .mask = (m) #endif /* __CROS_EC_CONFIG_CHIP_H */ diff --git a/chip/nrf51/gpio.c b/chip/nrf51/gpio.c index 3ad55f2b38..a01ee49940 100644 --- a/chip/nrf51/gpio.c +++ b/chip/nrf51/gpio.c @@ -164,7 +164,7 @@ void gpio_set_alternate_function(uint32_t port, uint32_t mask, int func) { uint32_t bit = GPIO_MASK_TO_NUM(mask); - ASSERT((~mask & (1 << bit)) == 0); /* Only one bit set. */ + ASSERT((~mask & BIT(bit)) == 0); /* Only one bit set. */ ASSERT(port == GPIO_0); ASSERT((func >= 0 && func < nrf51_alt_func_count) || func == -1); diff --git a/chip/nrf51/ppi.c b/chip/nrf51/ppi.c index d0be87f2ba..016cbf3008 100644 --- a/chip/nrf51/ppi.c +++ b/chip/nrf51/ppi.c @@ -18,10 +18,10 @@ int ppi_request_pre_programmed_channel(int ppi_chan) ASSERT(ppi_chan >= NRF51_PPI_FIRST_PP_CH && ppi_chan <= NRF51_PPI_LAST_PP_CH); - if (channels_in_use & (1 << ppi_chan)) + if (channels_in_use & BIT(ppi_chan)) return EC_ERROR_BUSY; - channels_in_use |= (1 << ppi_chan); + channels_in_use |= BIT(ppi_chan); return EC_SUCCESS; } @@ -31,25 +31,25 @@ int ppi_request_channel(int *ppi_chan) int chan; for (chan = 0; chan < NRF51_PPI_NUM_PROGRAMMABLE_CHANNELS; chan++) - if ((channels_in_use & (1 << chan)) == 0) + if ((channels_in_use & BIT(chan)) == 0) break; if (chan == NRF51_PPI_NUM_PROGRAMMABLE_CHANNELS) return EC_ERROR_BUSY; - channels_in_use |= (1 << chan); + channels_in_use |= BIT(chan); *ppi_chan = chan; return EC_SUCCESS; } void ppi_release_channel(int ppi_chan) { - channels_in_use &= ~(1 << ppi_chan); + channels_in_use &= ~BIT(ppi_chan); } void ppi_release_group(int ppi_group) { - channel_groups_in_use &= ~(1 << ppi_group); + channel_groups_in_use &= ~BIT(ppi_group); } int ppi_request_group(int *ppi_group) @@ -57,13 +57,13 @@ int ppi_request_group(int *ppi_group) int group; for (group = 0; group < NRF51_PPI_NUM_GROUPS; group++) - if ((channel_groups_in_use & (1 << group)) == 0) + if ((channel_groups_in_use & BIT(group)) == 0) break; if (group == NRF51_PPI_NUM_GROUPS) return EC_ERROR_BUSY; - channel_groups_in_use |= (1 << group); + channel_groups_in_use |= BIT(group); *ppi_group = group; return EC_SUCCESS; } diff --git a/chip/nrf51/radio_test.c b/chip/nrf51/radio_test.c index 5afb30425b..6c20874f4e 100644 --- a/chip/nrf51/radio_test.c +++ b/chip/nrf51/radio_test.c @@ -145,7 +145,7 @@ int ble_test_rx_init(int chan) int ble_test_tx_init(int chan, int len, int type) { - if (((1 << type) & BLE_TEST_TYPES_IMPLEMENTED) == 0 || + if ((BIT(type) & BLE_TEST_TYPES_IMPLEMENTED) == 0 || (len < 0 || len > BLE_MAX_TEST_PAYLOAD_OCTETS)) return HCI_ERR_Invalid_HCI_Command_Parameters; diff --git a/chip/nrf51/uart.c b/chip/nrf51/uart.c index ab52c6ad9a..eb94e53c98 100644 --- a/chip/nrf51/uart.c +++ b/chip/nrf51/uart.c @@ -34,13 +34,13 @@ void uart_tx_start(void) { disable_sleep(SLEEP_MASK_UART); should_stop = 0; - NRF51_UART_INTENSET = (1 << NRF55_UART_TXDRDY_BIT); + NRF51_UART_INTENSET = BIT(NRF55_UART_TXDRDY_BIT); task_trigger_irq(NRF51_PERID_USART); } void uart_tx_stop(void) { - NRF51_UART_INTENCLR = (1 << NRF55_UART_TXDRDY_BIT); + NRF51_UART_INTENCLR = BIT(NRF55_UART_TXDRDY_BIT); should_stop = 1; enable_sleep(SLEEP_MASK_UART); } @@ -96,7 +96,7 @@ void uart_interrupt(void) #ifndef CONFIG_UART_TX_DMA if (!should_stop) - NRF51_UART_INTENSET = (1 << NRF55_UART_TXDRDY_BIT); + NRF51_UART_INTENSET = BIT(NRF55_UART_TXDRDY_BIT); #endif /* CONFIG_UART_TX_DMA */ } @@ -113,7 +113,7 @@ void uart_init(void) task_enable_irq(NRF51_PERID_USART); - NRF51_UART_INTENSET = (1 << NRF55_UART_RXDRDY_BIT); + NRF51_UART_INTENSET = BIT(NRF55_UART_RXDRDY_BIT); NRF51_UART_STARTRX = 1; init_done = 1; diff --git a/chip/stm32/clock-stm32h7.c b/chip/stm32/clock-stm32h7.c index 30faa0035a..44d6e2e55a 100644 --- a/chip/stm32/clock-stm32h7.c +++ b/chip/stm32/clock-stm32h7.c @@ -32,7 +32,7 @@ * with /4 prescaler (2^2): period 125 us, full range ~8s */ #define LPTIM_PRESCALER_LOG2 2 -#define LPTIM_PRESCALER (1 << LPTIM_PRESCALER_LOG2) +#define LPTIM_PRESCALER BIT(LPTIM_PRESCALER_LOG2) #define LPTIM_PERIOD_US (SECOND / (STM32_LSI_CLOCK / LPTIM_PRESCALER)) /* diff --git a/chip/stm32/clock-stm32l.c b/chip/stm32/clock-stm32l.c index b0903b5cb1..2409e7918d 100644 --- a/chip/stm32/clock-stm32l.c +++ b/chip/stm32/clock-stm32l.c @@ -211,9 +211,9 @@ void clock_enable_module(enum module_id module, int enable) int new_mask; if (enable) - new_mask = clock_mask | (1 << module); + new_mask = clock_mask | BIT(module); else - new_mask = clock_mask & ~(1 << module); + new_mask = clock_mask & ~BIT(module); /* Only change clock if needed */ if ((!!new_mask) != (!!clock_mask)) { diff --git a/chip/stm32/clock-stm32l4.c b/chip/stm32/clock-stm32l4.c index c9042d10c4..182abcafca 100644 --- a/chip/stm32/clock-stm32l4.c +++ b/chip/stm32/clock-stm32l4.c @@ -324,9 +324,9 @@ void clock_enable_module(enum module_id module, int enable) int new_mask; if (enable) - new_mask = clock_mask | (1 << module); + new_mask = clock_mask | BIT(module); else - new_mask = clock_mask & ~(1 << module); + new_mask = clock_mask & ~BIT(module); /* Only change clock if needed */ if ((!!new_mask) != (!!clock_mask)) { diff --git a/chip/stm32/config_chip.h b/chip/stm32/config_chip.h index 0305197996..99cbd9b2be 100644 --- a/chip/stm32/config_chip.h +++ b/chip/stm32/config_chip.h @@ -140,7 +140,7 @@ #define CONFIG_CHIP_PRE_INIT #define GPIO_NAME_BY_PIN(port, index) #port#index -#define GPIO_PIN(port, index) GPIO_##port, (1 << index) +#define GPIO_PIN(port, index) GPIO_##port, BIT(index) #define GPIO_PIN_MASK(p, m) .port = GPIO_##p, .mask = (m) /* Prescaler values for PLL. Currently used only by STM32L476. */ diff --git a/chip/stm32/dma.c b/chip/stm32/dma.c index 26dfa0f823..e18676876f 100644 --- a/chip/stm32/dma.c +++ b/chip/stm32/dma.c @@ -65,7 +65,7 @@ void dma_select_channel(enum dma_channel channel, unsigned char stream) /* Local channel # starting from 0 on each DMA controller */ const unsigned char ch = channel % STM32_DMAC_PER_CTLR; const unsigned char shift = STM32_DMA_PERIPHERALS_PER_CHANNEL; - const unsigned char mask = (1 << shift) - 1; + const unsigned char mask = BIT(shift) - 1; uint32_t val; ASSERT(ch < STM32_DMAC_PER_CTLR); diff --git a/chip/stm32/flash-f.c b/chip/stm32/flash-f.c index aaf8e69873..8518485caa 100644 --- a/chip/stm32/flash-f.c +++ b/chip/stm32/flash-f.c @@ -442,7 +442,7 @@ int flash_physical_protect_at_boot(uint32_t new_flags) #endif if (protect) - val &= ~(1 << block); + val &= ~BIT(block); else val |= 1 << block; } diff --git a/chip/stm32/flash-stm32f0.c b/chip/stm32/flash-stm32f0.c index 6472b3e23b..e2ff2c779c 100644 --- a/chip/stm32/flash-stm32f0.c +++ b/chip/stm32/flash-stm32f0.c @@ -15,7 +15,7 @@ int flash_physical_get_protect(int block) { - return !(STM32_FLASH_WRPR & (1 << block)); + return !(STM32_FLASH_WRPR & BIT(block)); } /* diff --git a/chip/stm32/flash-stm32f3.c b/chip/stm32/flash-stm32f3.c index 843bbf48e4..ab505a082b 100644 --- a/chip/stm32/flash-stm32f3.c +++ b/chip/stm32/flash-stm32f3.c @@ -88,7 +88,7 @@ int flash_physical_get_protect(int block) { return (entire_flash_locked || #if defined(CHIP_FAMILY_STM32F3) - !(STM32_FLASH_WRPR & (1 << block)) + !(STM32_FLASH_WRPR & BIT(block)) #elif defined(CHIP_FAMILY_STM32F4) !(STM32_OPTB_WP & STM32_OPTB_nWRP(block)) #endif diff --git a/chip/stm32/flash-stm32h7.c b/chip/stm32/flash-stm32h7.c index 0f82bf409a..ba0a8a69f1 100644 --- a/chip/stm32/flash-stm32h7.c +++ b/chip/stm32/flash-stm32h7.c @@ -46,7 +46,7 @@ */ #define HWBANK_SIZE (CONFIG_FLASH_SIZE / 2) #define BLOCKS_PER_HWBANK (HWBANK_SIZE / CONFIG_FLASH_ERASE_SIZE) -#define BLOCKS_HWBANK_MASK ((1 << BLOCKS_PER_HWBANK) - 1) +#define BLOCKS_HWBANK_MASK (BIT(BLOCKS_PER_HWBANK) - 1) /* * We can tune the power consumption vs erase/write speed @@ -358,7 +358,7 @@ int flash_physical_get_protect(int block) int bank = block / BLOCKS_PER_HWBANK; int index = block % BLOCKS_PER_HWBANK; - return !(STM32_FLASH_WPSN_CUR(bank) & (1 << index)); + return !(STM32_FLASH_WPSN_CUR(bank) & BIT(index)); } /* diff --git a/chip/stm32/flash-stm32l.c b/chip/stm32/flash-stm32l.c index f796f4efaa..61916abf2d 100644 --- a/chip/stm32/flash-stm32l.c +++ b/chip/stm32/flash-stm32l.c @@ -314,13 +314,13 @@ int flash_physical_get_protect(int block) return 1; /* Check the active write protect status */ - return STM32_FLASH_WRPR & (1 << block); + return STM32_FLASH_WRPR & BIT(block); } int flash_physical_protect_at_boot(uint32_t new_flags) { uint32_t prot; - uint32_t mask = ((1 << WP_BANK_COUNT) - 1) << WP_BANK_OFFSET; + uint32_t mask = (BIT(WP_BANK_COUNT) - 1) << WP_BANK_OFFSET; int rv; if (new_flags & EC_FLASH_PROTECT_ALL_AT_BOOT) diff --git a/chip/stm32/pwm.c b/chip/stm32/pwm.c index 45d489a8c0..123c09968a 100644 --- a/chip/stm32/pwm.c +++ b/chip/stm32/pwm.c @@ -43,7 +43,7 @@ static void pwm_configure(enum pwm_channel ch) int frequency = pwm->frequency ? pwm->frequency : 100; uint16_t ccer; - if (using_pwm & (1 << ch)) + if (using_pwm & BIT(ch)) return; /* Enable timer */ @@ -109,7 +109,7 @@ static void pwm_disable(enum pwm_channel ch) const struct pwm_t *pwm = pwm_channels + ch; timer_ctlr_t *tim = (timer_ctlr_t *)(pwm->tim.base); - if ((using_pwm & (1 << ch)) == 0) + if ((using_pwm & BIT(ch)) == 0) return; /* Main output disable */ @@ -141,7 +141,7 @@ void pwm_enable(enum pwm_channel ch, int enabled) int pwm_get_enabled(enum pwm_channel ch) { - return using_pwm & (1 << ch); + return using_pwm & BIT(ch); } static void pwm_reconfigure(enum pwm_channel ch) diff --git a/chip/stm32/usb_dwc_registers.h b/chip/stm32/usb_dwc_registers.h index f8b90c1d1f..faac9ca775 100644 --- a/chip/stm32/usb_dwc_registers.h +++ b/chip/stm32/usb_dwc_registers.h @@ -175,13 +175,13 @@ extern struct dwc_usb usb_ctl; #define GR_USB_DOEPDMA(n) GR_USB_EPOREG(0x14, n) #define GR_USB_DOEPDMAB(n) GR_USB_EPOREG(0x1c, n) -#define GOTGCTL_BVALOEN (1 << GC_USB_GOTGCTL_BVALIDOVEN_LSB) +#define GOTGCTL_BVALOEN BIT(GC_USB_GOTGCTL_BVALIDOVEN_LSB) #define GOTGCTL_BVALOVAL BIT(7) /* Bit 5 */ -#define GAHBCFG_DMA_EN (1 << GC_USB_GAHBCFG_DMAEN_LSB) +#define GAHBCFG_DMA_EN BIT(GC_USB_GAHBCFG_DMAEN_LSB) /* Bit 1 */ -#define GAHBCFG_GLB_INTR_EN (1 << GC_USB_GAHBCFG_GLBLINTRMSK_LSB) +#define GAHBCFG_GLB_INTR_EN BIT(GC_USB_GAHBCFG_GLBLINTRMSK_LSB) /* HS Burst Len */ #define GAHBCFG_HBSTLEN_INCR4 (3 << GC_USB_GAHBCFG_HBSTLEN_LSB) /* Bit 7 */ @@ -194,7 +194,7 @@ extern struct dwc_usb usb_ctl; #define GUSBCFG_USBTRDTIM(n) (((n) << GC_USB_GUSBCFG_USBTRDTIM_LSB) \ & GC_USB_GUSBCFG_USBTRDTIM_MASK) /* Force device mode */ -#define GUSBCFG_FDMOD (1 << GC_USB_GUSBCFG_FDMOD_LSB) +#define GUSBCFG_FDMOD BIT(GC_USB_GUSBCFG_FDMOD_LSB) #define GUSBCFG_PHYSEL BIT(6) #define GUSBCFG_SRPCAP BIT(8) #define GUSBCFG_HNPCAP BIT(9) @@ -210,81 +210,81 @@ extern struct dwc_usb usb_ctl; #define GUSBCFG_TSDPS BIT(22) -#define GRSTCTL_CSFTRST (1 << GC_USB_GRSTCTL_CSFTRST_LSB) -#define GRSTCTL_AHBIDLE (1 << GC_USB_GRSTCTL_AHBIDLE_LSB) -#define GRSTCTL_TXFFLSH (1 << GC_USB_GRSTCTL_TXFFLSH_LSB) -#define GRSTCTL_RXFFLSH (1 << GC_USB_GRSTCTL_RXFFLSH_LSB) +#define GRSTCTL_CSFTRST BIT(GC_USB_GRSTCTL_CSFTRST_LSB) +#define GRSTCTL_AHBIDLE BIT(GC_USB_GRSTCTL_AHBIDLE_LSB) +#define GRSTCTL_TXFFLSH BIT(GC_USB_GRSTCTL_TXFFLSH_LSB) +#define GRSTCTL_RXFFLSH BIT(GC_USB_GRSTCTL_RXFFLSH_LSB) #define GRSTCTL_TXFNUM(n) \ (((n) << GC_USB_GRSTCTL_TXFNUM_LSB) & GC_USB_GRSTCTL_TXFNUM_MASK) #define DCFG_DEVSPD_HSULPI (0 << GC_USB_DCFG_DEVSPD_LSB) -#define DCFG_DEVSPD_FSULPI (1 << GC_USB_DCFG_DEVSPD_LSB) +#define DCFG_DEVSPD_FSULPI BIT(GC_USB_DCFG_DEVSPD_LSB) #define DCFG_DEVSPD_FS48 (3 << GC_USB_DCFG_DEVSPD_LSB) #define DCFG_DEVADDR(a) \ (((a) << GC_USB_DCFG_DEVADDR_LSB) & GC_USB_DCFG_DEVADDR_MASK) -#define DCFG_NZLSOHSK (1 << GC_USB_DCFG_NZSTSOUTHSHK_LSB) +#define DCFG_NZLSOHSK BIT(GC_USB_DCFG_NZSTSOUTHSHK_LSB) -#define DCTL_SFTDISCON (1 << GC_USB_DCTL_SFTDISCON_LSB) -#define DCTL_CGOUTNAK (1 << GC_USB_DCTL_CGOUTNAK_LSB) -#define DCTL_CGNPINNAK (1 << GC_USB_DCTL_CGNPINNAK_LSB) -#define DCTL_PWRONPRGDONE (1 << GC_USB_DCTL_PWRONPRGDONE_LSB) +#define DCTL_SFTDISCON BIT(GC_USB_DCTL_SFTDISCON_LSB) +#define DCTL_CGOUTNAK BIT(GC_USB_DCTL_CGOUTNAK_LSB) +#define DCTL_CGNPINNAK BIT(GC_USB_DCTL_CGNPINNAK_LSB) +#define DCTL_PWRONPRGDONE BIT(GC_USB_DCTL_PWRONPRGDONE_LSB) /* Device Endpoint Common IN Interrupt Mask bits */ -#define DIEPMSK_AHBERRMSK (1 << GC_USB_DIEPMSK_AHBERRMSK_LSB) -#define DIEPMSK_BNAININTRMSK (1 << GC_USB_DIEPMSK_BNAININTRMSK_LSB) -#define DIEPMSK_EPDISBLDMSK (1 << GC_USB_DIEPMSK_EPDISBLDMSK_LSB) -#define DIEPMSK_INEPNAKEFFMSK (1 << GC_USB_DIEPMSK_INEPNAKEFFMSK_LSB) -#define DIEPMSK_INTKNEPMISMSK (1 << GC_USB_DIEPMSK_INTKNEPMISMSK_LSB) -#define DIEPMSK_INTKNTXFEMPMSK (1 << GC_USB_DIEPMSK_INTKNTXFEMPMSK_LSB) -#define DIEPMSK_NAKMSK (1 << GC_USB_DIEPMSK_NAKMSK_LSB) -#define DIEPMSK_TIMEOUTMSK (1 << GC_USB_DIEPMSK_TIMEOUTMSK_LSB) -#define DIEPMSK_TXFIFOUNDRNMSK (1 << GC_USB_DIEPMSK_TXFIFOUNDRNMSK_LSB) -#define DIEPMSK_XFERCOMPLMSK (1 << GC_USB_DIEPMSK_XFERCOMPLMSK_LSB) +#define DIEPMSK_AHBERRMSK BIT(GC_USB_DIEPMSK_AHBERRMSK_LSB) +#define DIEPMSK_BNAININTRMSK BIT(GC_USB_DIEPMSK_BNAININTRMSK_LSB) +#define DIEPMSK_EPDISBLDMSK BIT(GC_USB_DIEPMSK_EPDISBLDMSK_LSB) +#define DIEPMSK_INEPNAKEFFMSK BIT(GC_USB_DIEPMSK_INEPNAKEFFMSK_LSB) +#define DIEPMSK_INTKNEPMISMSK BIT(GC_USB_DIEPMSK_INTKNEPMISMSK_LSB) +#define DIEPMSK_INTKNTXFEMPMSK BIT(GC_USB_DIEPMSK_INTKNTXFEMPMSK_LSB) +#define DIEPMSK_NAKMSK BIT(GC_USB_DIEPMSK_NAKMSK_LSB) +#define DIEPMSK_TIMEOUTMSK BIT(GC_USB_DIEPMSK_TIMEOUTMSK_LSB) +#define DIEPMSK_TXFIFOUNDRNMSK BIT(GC_USB_DIEPMSK_TXFIFOUNDRNMSK_LSB) +#define DIEPMSK_XFERCOMPLMSK BIT(GC_USB_DIEPMSK_XFERCOMPLMSK_LSB) /* Device Endpoint Common OUT Interrupt Mask bits */ -#define DOEPMSK_AHBERRMSK (1 << GC_USB_DOEPMSK_AHBERRMSK_LSB) -#define DOEPMSK_BBLEERRMSK (1 << GC_USB_DOEPMSK_BBLEERRMSK_LSB) -#define DOEPMSK_BNAOUTINTRMSK (1 << GC_USB_DOEPMSK_BNAOUTINTRMSK_LSB) -#define DOEPMSK_EPDISBLDMSK (1 << GC_USB_DOEPMSK_EPDISBLDMSK_LSB) -#define DOEPMSK_NAKMSK (1 << GC_USB_DOEPMSK_NAKMSK_LSB) -#define DOEPMSK_NYETMSK (1 << GC_USB_DOEPMSK_NYETMSK_LSB) -#define DOEPMSK_OUTPKTERRMSK (1 << GC_USB_DOEPMSK_OUTPKTERRMSK_LSB) -#define DOEPMSK_OUTTKNEPDISMSK (1 << GC_USB_DOEPMSK_OUTTKNEPDISMSK_LSB) -#define DOEPMSK_SETUPMSK (1 << GC_USB_DOEPMSK_SETUPMSK_LSB) -#define DOEPMSK_STSPHSERCVDMSK (1 << GC_USB_DOEPMSK_STSPHSERCVDMSK_LSB) -#define DOEPMSK_XFERCOMPLMSK (1 << GC_USB_DOEPMSK_XFERCOMPLMSK_LSB) +#define DOEPMSK_AHBERRMSK BIT(GC_USB_DOEPMSK_AHBERRMSK_LSB) +#define DOEPMSK_BBLEERRMSK BIT(GC_USB_DOEPMSK_BBLEERRMSK_LSB) +#define DOEPMSK_BNAOUTINTRMSK BIT(GC_USB_DOEPMSK_BNAOUTINTRMSK_LSB) +#define DOEPMSK_EPDISBLDMSK BIT(GC_USB_DOEPMSK_EPDISBLDMSK_LSB) +#define DOEPMSK_NAKMSK BIT(GC_USB_DOEPMSK_NAKMSK_LSB) +#define DOEPMSK_NYETMSK BIT(GC_USB_DOEPMSK_NYETMSK_LSB) +#define DOEPMSK_OUTPKTERRMSK BIT(GC_USB_DOEPMSK_OUTPKTERRMSK_LSB) +#define DOEPMSK_OUTTKNEPDISMSK BIT(GC_USB_DOEPMSK_OUTTKNEPDISMSK_LSB) +#define DOEPMSK_SETUPMSK BIT(GC_USB_DOEPMSK_SETUPMSK_LSB) +#define DOEPMSK_STSPHSERCVDMSK BIT(GC_USB_DOEPMSK_STSPHSERCVDMSK_LSB) +#define DOEPMSK_XFERCOMPLMSK BIT(GC_USB_DOEPMSK_XFERCOMPLMSK_LSB) /* Device Endpoint-n IN Interrupt Register bits */ -#define DIEPINT_AHBERR (1 << GC_USB_DIEPINT0_AHBERR_LSB) -#define DIEPINT_BBLEERR (1 << GC_USB_DIEPINT0_BBLEERR_LSB) -#define DIEPINT_BNAINTR (1 << GC_USB_DIEPINT0_BNAINTR_LSB) -#define DIEPINT_EPDISBLD (1 << GC_USB_DIEPINT0_EPDISBLD_LSB) -#define DIEPINT_INEPNAKEFF (1 << GC_USB_DIEPINT0_INEPNAKEFF_LSB) -#define DIEPINT_INTKNEPMIS (1 << GC_USB_DIEPINT0_INTKNEPMIS_LSB) -#define DIEPINT_INTKNTXFEMP (1 << GC_USB_DIEPINT0_INTKNTXFEMP_LSB) -#define DIEPINT_NAKINTRPT (1 << GC_USB_DIEPINT0_NAKINTRPT_LSB) -#define DIEPINT_NYETINTRPT (1 << GC_USB_DIEPINT0_NYETINTRPT_LSB) -#define DIEPINT_PKTDRPSTS (1 << GC_USB_DIEPINT0_PKTDRPSTS_LSB) -#define DIEPINT_TIMEOUT (1 << GC_USB_DIEPINT0_TIMEOUT_LSB) -#define DIEPINT_TXFEMP (1 << GC_USB_DIEPINT0_TXFEMP_LSB) -#define DIEPINT_TXFIFOUNDRN (1 << GC_USB_DIEPINT0_TXFIFOUNDRN_LSB) -#define DIEPINT_XFERCOMPL (1 << GC_USB_DIEPINT0_XFERCOMPL_LSB) +#define DIEPINT_AHBERR BIT(GC_USB_DIEPINT0_AHBERR_LSB) +#define DIEPINT_BBLEERR BIT(GC_USB_DIEPINT0_BBLEERR_LSB) +#define DIEPINT_BNAINTR BIT(GC_USB_DIEPINT0_BNAINTR_LSB) +#define DIEPINT_EPDISBLD BIT(GC_USB_DIEPINT0_EPDISBLD_LSB) +#define DIEPINT_INEPNAKEFF BIT(GC_USB_DIEPINT0_INEPNAKEFF_LSB) +#define DIEPINT_INTKNEPMIS BIT(GC_USB_DIEPINT0_INTKNEPMIS_LSB) +#define DIEPINT_INTKNTXFEMP BIT(GC_USB_DIEPINT0_INTKNTXFEMP_LSB) +#define DIEPINT_NAKINTRPT BIT(GC_USB_DIEPINT0_NAKINTRPT_LSB) +#define DIEPINT_NYETINTRPT BIT(GC_USB_DIEPINT0_NYETINTRPT_LSB) +#define DIEPINT_PKTDRPSTS BIT(GC_USB_DIEPINT0_PKTDRPSTS_LSB) +#define DIEPINT_TIMEOUT BIT(GC_USB_DIEPINT0_TIMEOUT_LSB) +#define DIEPINT_TXFEMP BIT(GC_USB_DIEPINT0_TXFEMP_LSB) +#define DIEPINT_TXFIFOUNDRN BIT(GC_USB_DIEPINT0_TXFIFOUNDRN_LSB) +#define DIEPINT_XFERCOMPL BIT(GC_USB_DIEPINT0_XFERCOMPL_LSB) /* Device Endpoint-n OUT Interrupt Register bits */ -#define DOEPINT_AHBERR (1 << GC_USB_DOEPINT0_AHBERR_LSB) -#define DOEPINT_BACK2BACKSETUP (1 << GC_USB_DOEPINT0_BACK2BACKSETUP_LSB) -#define DOEPINT_BBLEERR (1 << GC_USB_DOEPINT0_BBLEERR_LSB) -#define DOEPINT_BNAINTR (1 << GC_USB_DOEPINT0_BNAINTR_LSB) -#define DOEPINT_EPDISBLD (1 << GC_USB_DOEPINT0_EPDISBLD_LSB) -#define DOEPINT_NAKINTRPT (1 << GC_USB_DOEPINT0_NAKINTRPT_LSB) -#define DOEPINT_NYETINTRPT (1 << GC_USB_DOEPINT0_NYETINTRPT_LSB) -#define DOEPINT_OUTPKTERR (1 << GC_USB_DOEPINT0_OUTPKTERR_LSB) -#define DOEPINT_OUTTKNEPDIS (1 << GC_USB_DOEPINT0_OUTTKNEPDIS_LSB) -#define DOEPINT_PKTDRPSTS (1 << GC_USB_DOEPINT0_PKTDRPSTS_LSB) -#define DOEPINT_SETUP (1 << GC_USB_DOEPINT0_SETUP_LSB) -#define DOEPINT_STSPHSERCVD (1 << GC_USB_DOEPINT0_STSPHSERCVD_LSB) -#define DOEPINT_STUPPKTRCVD (1 << GC_USB_DOEPINT0_STUPPKTRCVD_LSB) -#define DOEPINT_XFERCOMPL (1 << GC_USB_DOEPINT0_XFERCOMPL_LSB) +#define DOEPINT_AHBERR BIT(GC_USB_DOEPINT0_AHBERR_LSB) +#define DOEPINT_BACK2BACKSETUP BIT(GC_USB_DOEPINT0_BACK2BACKSETUP_LSB) +#define DOEPINT_BBLEERR BIT(GC_USB_DOEPINT0_BBLEERR_LSB) +#define DOEPINT_BNAINTR BIT(GC_USB_DOEPINT0_BNAINTR_LSB) +#define DOEPINT_EPDISBLD BIT(GC_USB_DOEPINT0_EPDISBLD_LSB) +#define DOEPINT_NAKINTRPT BIT(GC_USB_DOEPINT0_NAKINTRPT_LSB) +#define DOEPINT_NYETINTRPT BIT(GC_USB_DOEPINT0_NYETINTRPT_LSB) +#define DOEPINT_OUTPKTERR BIT(GC_USB_DOEPINT0_OUTPKTERR_LSB) +#define DOEPINT_OUTTKNEPDIS BIT(GC_USB_DOEPINT0_OUTTKNEPDIS_LSB) +#define DOEPINT_PKTDRPSTS BIT(GC_USB_DOEPINT0_PKTDRPSTS_LSB) +#define DOEPINT_SETUP BIT(GC_USB_DOEPINT0_SETUP_LSB) +#define DOEPINT_STSPHSERCVD BIT(GC_USB_DOEPINT0_STSPHSERCVD_LSB) +#define DOEPINT_STUPPKTRCVD BIT(GC_USB_DOEPINT0_STUPPKTRCVD_LSB) +#define DOEPINT_XFERCOMPL BIT(GC_USB_DOEPINT0_XFERCOMPL_LSB) #define DXEPCTL_EPTYPE_CTRL (0 << GC_USB_DIEPCTL0_EPTYPE_LSB) #define DXEPCTL_EPTYPE_ISO (1 << GC_USB_DIEPCTL0_EPTYPE_LSB) @@ -292,14 +292,14 @@ extern struct dwc_usb usb_ctl; #define DXEPCTL_EPTYPE_INT (3 << GC_USB_DIEPCTL0_EPTYPE_LSB) #define DXEPCTL_EPTYPE_MASK GC_USB_DIEPCTL0_EPTYPE_MASK #define DXEPCTL_TXFNUM(n) ((n) << GC_USB_DIEPCTL1_TXFNUM_LSB) -#define DXEPCTL_STALL (1 << GC_USB_DIEPCTL0_STALL_LSB) -#define DXEPCTL_CNAK (1 << GC_USB_DIEPCTL0_CNAK_LSB) -#define DXEPCTL_DPID (1 << GC_USB_DIEPCTL0_DPID_LSB) -#define DXEPCTL_SNAK (1 << GC_USB_DIEPCTL0_SNAK_LSB) -#define DXEPCTL_NAKSTS (1 << GC_USB_DIEPCTL0_NAKSTS_LSB) -#define DXEPCTL_EPENA (1 << GC_USB_DIEPCTL0_EPENA_LSB) -#define DXEPCTL_EPDIS (1 << GC_USB_DIEPCTL0_EPDIS_LSB) -#define DXEPCTL_USBACTEP (1 << GC_USB_DIEPCTL0_USBACTEP_LSB) +#define DXEPCTL_STALL BIT(GC_USB_DIEPCTL0_STALL_LSB) +#define DXEPCTL_CNAK BIT(GC_USB_DIEPCTL0_CNAK_LSB) +#define DXEPCTL_DPID BIT(GC_USB_DIEPCTL0_DPID_LSB) +#define DXEPCTL_SNAK BIT(GC_USB_DIEPCTL0_SNAK_LSB) +#define DXEPCTL_NAKSTS BIT(GC_USB_DIEPCTL0_NAKSTS_LSB) +#define DXEPCTL_EPENA BIT(GC_USB_DIEPCTL0_EPENA_LSB) +#define DXEPCTL_EPDIS BIT(GC_USB_DIEPCTL0_EPDIS_LSB) +#define DXEPCTL_USBACTEP BIT(GC_USB_DIEPCTL0_USBACTEP_LSB) #define DXEPCTL_MPS64 (0 << GC_USB_DIEPCTL0_MPS_LSB) #define DXEPCTL_MPS(cnt) ((cnt) << GC_USB_DIEPCTL1_MPS_LSB) |