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authorHyungwoo Yang <hyungwoo.yang@intel.com>2019-04-15 22:17:11 -0700
committerchrome-bot <chrome-bot@chromium.org>2019-04-26 04:19:18 -0700
commitf730c0c1ab2cadb820676ef09ebb57888d48cb96 (patch)
tree8953f42e6776f828c0f55cc2c01d44c087a43511 /chip
parent6549da39d519b4d07e8bca7bef0393549765412b (diff)
downloadchrome-ec-f730c0c1ab2cadb820676ef09ebb57888d48cb96.tar.gz
ish: fix s/w generated interrupt request
Current s/w generated IRQ uses LAPIC's ICR but it causes pending interrupts for other IRQs in IOAPIC and leads LVT error with illegal vector. So instead of using ICR, we use "int" instruction. BRANCH=none BUG=b:129937881,b:124128140 TEST=Tested on Arcada platform Change-Id: I49c4120e7355f9a98d20d5ed259c4fdf6bad5196 Signed-off-by: Hyungwoo Yang <hyungwoo.yang@intel.com> Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1568786 Commit-Ready: Jack Rosenthal <jrosenth@chromium.org> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
Diffstat (limited to 'chip')
-rw-r--r--chip/ish/registers.h3
1 files changed, 2 insertions, 1 deletions
diff --git a/chip/ish/registers.h b/chip/ish/registers.h
index 592f09b991..03aac276fb 100644
--- a/chip/ish/registers.h
+++ b/chip/ish/registers.h
@@ -94,7 +94,8 @@ enum ish_i2c_port {
/* APIC interrupt vectors */
#define ISH_TS_VECTOR 0x20 /* Task switch vector */
-#define LAPIC_LVT_ERROR_VECTOR 0x21
+#define LAPIC_LVT_ERROR_VECTOR 0x21 /* Clears IOAPIC/LAPIC sync errors */
+#define SOFTIRQ_VECTOR 0x22 /* Handles software generated IRQs */
#define LAPIC_SPURIOUS_INT_VECTOR 0xff
/* Interrupt to vector mapping. To be programmed into IOAPIC */