chip/it8xxx2: add support IT81302 and IT81202

IT81302 (144-pins package) and IT81202 (128-pins package) chips belong
to it8xxx2 family. So we apply the same chip options of it83202bx
(except ADC pin order config option) and setup the correct flash size,
ram size, and ram base.

With this change, we are able to build FW image with IT81202 or IT81302
chip variant.

BUG=none
BRANCH=none
TEST=EC boots and test console commands
     (version, sysinfo, sysjump, flasherase, flashwrite, and flashread)
     on IT81202 EVB.
     Hibernate EC and then press servo board's COLD_RST_L to reset EC.
     EC reboots.

Change-Id: If351d561c61f635ebdb1e4e444e73e061a494c9a
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2072562
Reviewed-by: Jett Rink <jettrink@chromium.org>

3 files changed, 59 insertions, 6 deletions

diff --git a/chip/it83xx/config_chip_it8xxx2.h b/chip/it83xx/config_chip_it8xxx2.h
index 036736fd70..ae6388e8c4 100644
--- a/chip/it83xx/config_chip_it8xxx2.h
+++ b/chip/it83xx/config_chip_it8xxx2.h
@@ -19,15 +19,9 @@
 /* Memory mapping */
 
 #define CHIP_ILM_BASE               0x80000000
-#define CHIP_H2RAM_BASE             0x80081000 /* 0x80081000~0x80081FFF */
-#define CHIP_RAMCODE_BASE           0x80082000 /* 0x80082000~0x80082FFF */
 #define CHIP_EXTRA_STACK_SPACE      128
 /* We reserve 12KB space for ramcode, h2ram, and immu sections. */
 #define CHIP_RAM_SPACE_RESERVED     0x3000
-
-#define CONFIG_RAM_BASE             0x80080000
-#define CONFIG_RAM_SIZE             0x00010000
-
 #define CONFIG_PROGRAM_MEMORY_BASE  (CHIP_ILM_BASE)
 
 /****************************************************************************/
@@ -37,6 +31,8 @@
 #if defined(CHIP_VARIANT_IT83202BX)
 /* TODO(b/133460224): enable properly chip config option. */
 #define CONFIG_FLASH_SIZE           0x00080000
+#define CONFIG_RAM_BASE             0x80080000
+#define CONFIG_RAM_SIZE             0x00010000
 /*
  * ADC control pin order change:
  * ADC13 control pin GPL0               GPL1
@@ -52,6 +48,11 @@
 /* chip id is 3 bytes */
 #define IT83XX_CHIP_ID_3BYTES
 /*
+ * The bit19 of ram code base address is controlled by bit7 of register SCARxH
+ * instead of bit3.
+ */
+#define IT83XX_DAM_ADDR_BIT19_AT_REG_SCARXH_BIT7
+/*
  * Disable eSPI pad, then PLL change
  * (include EC clock frequency) is succeed even CS# is low.
  */
@@ -71,8 +72,48 @@
 #define IT83XX_INTC_PLUG_IN_SUPPORT
 /* Chip IT83202BX actually has TCPC physical port count. */
 #define IT83XX_USBPD_PHY_PORT_COUNT    3
+#elif defined(CHIP_VARIANT_IT81302AX_1024) \
+|| defined(CHIP_VARIANT_IT81202AX_1024)
+#define CONFIG_FLASH_SIZE           0x00100000
+#define CONFIG_RAM_BASE             0x80100000
+#define CONFIG_RAM_SIZE             0x0000f000
+
+/* Embedded flash is KGD */
+#define IT83XX_CHIP_FLASH_IS_KGD
+/* Set ILM (instruction local memory) size up to 1M bytes */
+#define IT83XX_CHIP_FLASH_SIZE_1MB
+/* chip id is 3 bytes */
+#define IT83XX_CHIP_ID_3BYTES
+/*
+ * The bit19 of ram code base address is controlled by bit7 of register SCARxH
+ * instead of bit3.
+ */
+#define IT83XX_DAM_ADDR_BIT19_AT_REG_SCARXH_BIT7
+/*
+ * Disable eSPI pad, then PLL change
+ * (include EC clock frequency) is succeed even CS# is low.
+ */
+#define IT83XX_ESPI_INHIBIT_CS_BY_PAD_DISABLED
+/* The slave frequency is adjustable (bit[2-0] at register IT83XX_ESPI_GCAC1) */
+#define IT83XX_ESPI_SLAVE_MAX_FREQ_CONFIGURABLE
+/* Watchdog reset supports hardware reset. */
+#define IT83XX_ETWD_HW_RESET_SUPPORT
+/*
+ * More GPIOs can be set as 1.8v input.
+ * Please refer to gpio_1p8v_sel[] for 1.8v GPIOs.
+ */
+#define IT83XX_GPIO_1P8V_PIN_EXTENDED
+/* All GPIOs support interrupt on rising, falling, and either edge. */
+#define IT83XX_GPIO_INT_FLEXIBLE
+/* Enable detect type-c plug in interrupt. */
+#define IT83XX_INTC_PLUG_IN_SUPPORT
+/* Chip actually has TCPC physical port count. */
+#define IT83XX_USBPD_PHY_PORT_COUNT    2
 #else
 #error "Unsupported chip variant!"
 #endif
 
+#define CHIP_H2RAM_BASE   (CONFIG_RAM_BASE + 0x1000) /* base+1000h~base+1FFF */
+#define CHIP_RAMCODE_BASE (CONFIG_RAM_BASE + 0x2000) /* base+2000h~base+2FFF */
+
 #endif  /* __CROS_EC_CONFIG_CHIP_IT8XXX2_H */
diff --git a/chip/it83xx/flash.c b/chip/it83xx/flash.c
index d40566f8ae..42fee49053 100644
--- a/chip/it83xx/flash.c
+++ b/chip/it83xx/flash.c
@@ -641,7 +641,15 @@ static void flash_code_static_dma(void)
 	 */
 	IT83XX_SMFI_SCAR2L = FLASH_DMA_START & 0xFF;
 	IT83XX_SMFI_SCAR2M = (FLASH_DMA_START >> 8) & 0xFF;
+#ifdef IT83XX_DAM_ADDR_BIT19_AT_REG_SCARXH_BIT7
+	IT83XX_SMFI_SCAR2H = (FLASH_DMA_START >> 16) & 0x7;
+	if (FLASH_DMA_START & BIT(19))
+		IT83XX_SMFI_SCAR2H |= BIT(7);
+	else
+		IT83XX_SMFI_SCAR2H &= ~BIT(7);
+#else
 	IT83XX_SMFI_SCAR2H = (FLASH_DMA_START >> 16) & 0x0F;
+#endif
 	/*
 	 * Validate Direct-map SRAM function by programming
 	 * register SCARx bit20=0
diff --git a/chip/it83xx/registers.h b/chip/it83xx/registers.h
index ff2467c606..2df14c9441 100644
--- a/chip/it83xx/registers.h
+++ b/chip/it83xx/registers.h
@@ -1297,7 +1297,11 @@ REG8(IT83XX_PMC_BASE + (ch > LPC_PM2 ? 5 : 8) + (ch << 4))
 #define IT83XX_SPI_RXFFSM          (BIT(4) | BIT(3))
 #define IT83XX_SPI_RXF2FS          BIT(2)
 #define IT83XX_SPI_RXF1FS          BIT(1)
+#ifdef CHIP_VARIANT_IT83202BX
 #define IT83XX_SPI_SPISRDR      REG8(IT83XX_SPI_BASE+0x08)
+#else
+#define IT83XX_SPI_SPISRDR      REG8(IT83XX_SPI_BASE+0x0b)
+#endif
 #define IT83XX_SPI_CPUWTFDB0    REG32(IT83XX_SPI_BASE+0x08)
 #define IT83XX_SPI_FCR          REG8(IT83XX_SPI_BASE+0x09)
 #define IT83XX_SPI_SPISRTXF        BIT(2)