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author | CHLin <CHLIN56@nuvoton.com> | 2016-12-08 11:02:23 +0800 |
---|---|---|
committer | ChromeOS Commit Bot <chromeos-commit-bot@chromium.org> | 2016-12-09 03:12:41 +0000 |
commit | 2cdc5427491b4f3263832ec6ea25e13218a8768f (patch) | |
tree | 8cfb7e603491b8f0b5cea2f40c3d382efbf2e502 /chip | |
parent | f89305bcc4e53b9d038efa9de18f22c773ecd8ea (diff) | |
download | chrome-ec-2cdc5427491b4f3263832ec6ea25e13218a8768f.tar.gz |
npcx: lpc: Fix KB malfunction after power-key off and then on
The original thought of setting LRESET_PLTRST_MODE to 1 is to remove the
need to reinitialize host module registers whenever LRESET# occurs in
order to save time when boot-up.
However, some of these registers will be reset by core domain reset. It
means every time LRESET is de-asserted, we need to initialize the host
setting again. Therefore, setting LRESET_PLTRST_MODE to 1 is unnecessary
and sometimes dangerous. If BIOS believes LRESET will reset ec's host
state machine to default but ec not, it will cause unexpected behavior.
Modified drivers:
1. lpc.c: allow LRESET/PLTRST generate host domain reset
BUG=chrome-os-partner:60211
BRANCH:none
TEST=make buildall. run "dut-control pwr_button:press; sleep 11; dut-control
pwr_button:release; sleep 7; dut-control pwr_button:press; sleep 1;
dut-control pwr_button:release". Verify keyboard works normally.
Change-Id: I94d428cde69f828468547c44844983f25686ea04
Signed-off-by: CHLin <CHLIN56@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/417745
Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org>
Tested-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/418456
Commit-Queue: Aaron Durbin <adurbin@chromium.org>
Tested-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'chip')
-rw-r--r-- | chip/npcx/lpc.c | 3 |
1 files changed, 0 insertions, 3 deletions
diff --git a/chip/npcx/lpc.c b/chip/npcx/lpc.c index 7f569af078..63507ce1f1 100644 --- a/chip/npcx/lpc.c +++ b/chip/npcx/lpc.c @@ -811,9 +811,6 @@ void host_register_init(void) /* enable SHM */ lpc_sib_write_reg(SIO_OFFSET, 0x30, 0x01); - /* An active LRESET or PLTRST does not generate host domain reset */ - SET_BIT(NPCX_RSTCTL, NPCX_RSTCTL_LRESET_PLTRST_MODE); - CPRINTS("Host settings are done!"); } |