diff options
| author | Dino Li <Dino.Li@ite.com.tw> | 2018-08-01 11:54:04 +0800 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2018-08-01 19:35:30 -0700 |
| commit | b755ac8b72774899dfe43f87e4a2df6cd8d6f840 (patch) | |
| tree | 74db61d7d4a9cc28d72743e6534529243e91c901 /chip | |
| parent | fe10a59e056643e3b23a5d1b0e6142323b0e5ced (diff) | |
| download | chrome-ec-b755ac8b72774899dfe43f87e4a2df6cd8d6f840.tar.gz | |
it83xx: Enable USB module's clock before set USB control register
symptom:
On bip, the PPC's INT pin is always asserted after we do a EC reboot
command.
This is because the setting of clock gating control register will
not be reset with a EC reboot command.
Clock gating control register only resets by EC's WRST# pin
BUG=b:111006203, b:110237505
BRANCH=none
TEST=The PPC's INT pin is deasserted after EC reboot command.
Change-Id: Icf62d5fb32c0d1d25aea03b7bfbcb032a60f31a1
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
Reviewed-on: https://chromium-review.googlesource.com/1154855
Reviewed-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
Diffstat (limited to 'chip')
| -rw-r--r-- | chip/it83xx/gpio.c | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/chip/it83xx/gpio.c b/chip/it83xx/gpio.c index ee1271f694..3709838f75 100644 --- a/chip/it83xx/gpio.c +++ b/chip/it83xx/gpio.c @@ -605,6 +605,13 @@ void gpio_pre_init(void) #ifndef CONFIG_USB /* + * We need to enable USB's clock so we can config USB control register. + * This is important for a software reset as the hardware clock may + * already be disabled from the previous run. + * We will disable clock to USB module in clock_module_disable() later. + */ + clock_enable_peripheral(CGC_OFFSET_USB, 0, 0); + /* * Disable default pull-down of USB controller (GPH5 and GPH6) if we * don't use this module. */ |