diff options
| author | Dino Li <Dino.Li@ite.com.tw> | 2018-06-05 14:41:03 +0800 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2018-06-06 01:16:12 -0700 |
| commit | 8290d879dab1fbba805cfcdb4f2409bdee803dc6 (patch) | |
| tree | 01de7c883b8e7d65bebd0dc842d39b46c5104465 /chip | |
| parent | c06b3916770535270faf790c43866708b433bfd4 (diff) | |
| download | chrome-ec-8290d879dab1fbba805cfcdb4f2409bdee803dc6.tar.gz | |
it83xx: espi: enable eSPI_reset#
With this patch, EC will reset peripheral, OOB message,
virtual wire, and flash access channels to default settings
while the eSPI_reset# pin is asserted.
BUG=b:80250980
BRANCH=none
TEST=ran console command `hibernate` or 'apshutdown' during system boot
to kernel and then wake system up by power button x 100.
Change-Id: Iceb7ddf1a045937c004f429fc46a7346578b0cce
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
Reviewed-on: https://chromium-review.googlesource.com/1074672
Tested-by: Stephanie Payton <stephie0128@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
Diffstat (limited to 'chip')
| -rw-r--r-- | chip/it83xx/espi.c | 34 | ||||
| -rw-r--r-- | chip/it83xx/intc.h | 1 |
2 files changed, 35 insertions, 0 deletions
diff --git a/chip/it83xx/espi.c b/chip/it83xx/espi.c index 6bd74fec1e..5f6d48f6b1 100644 --- a/chip/it83xx/espi.c +++ b/chip/it83xx/espi.c @@ -417,6 +417,37 @@ static void espi_reset_vw_index_flags(void) vw_index_flag[i] = IT83XX_ESPI_VWIDX(vw_isr_list[i].vw_index); } +void espi_reset_pin_asserted_interrupt(enum gpio_signal signal) +{ + /* reset vw_index_flag when espi_reset# asserted. */ + espi_reset_vw_index_flags(); +} + +static void espi_enable_reset(void) +{ + const struct gpio_info *espi_rst = gpio_list + GPIO_ESPI_RESET_L; + + /* + * bit[2-1]: + * 00b: reserved. + * 01b: espi_reset# is enabled on GPB7. + * 10b: espi_reset# is enabled on GPD2. + * 11b: reset is disabled. + */ + if (espi_rst->port == GPIO_D && espi_rst->mask == (1 << 2)) { + IT83XX_GPIO_GCR = (IT83XX_GPIO_GCR & ~0x6) | (1 << 2); + } else if (espi_rst->port == GPIO_B && espi_rst->mask == (1 << 7)) { + IT83XX_GPIO_GCR = (IT83XX_GPIO_GCR & ~0x6) | (1 << 1); + } else { + IT83XX_GPIO_GCR |= 0x6; + CPRINTS("EC's espi_reset pin is not enabled correctly"); + } + + /* enable interrupt of EC's espi_reset pin */ + gpio_clear_pending_interrupt(GPIO_ESPI_RESET_L); + gpio_enable_interrupt(GPIO_ESPI_RESET_L); +} + /* Interrupt event of master enables the VW channel. */ static void espi_vw_en_asserted(uint8_t evt) { @@ -515,4 +546,7 @@ void espi_init(void) /* bit4: eSPI to WUC enable */ IT83XX_ESPI_ESGCTRL2 |= (1 << 4); task_enable_irq(IT83XX_IRQ_ESPI); + + /* enable interrupt and reset from eSPI_reset# */ + espi_enable_reset(); } diff --git a/chip/it83xx/intc.h b/chip/it83xx/intc.h index b24d17fd2b..1b085498fc 100644 --- a/chip/it83xx/intc.h +++ b/chip/it83xx/intc.h @@ -21,6 +21,7 @@ void i2c_interrupt(int port); void clock_sleep_mode_wakeup_isr(void); int clock_ec_wake_from_sleep(void); void __enter_hibernate(uint32_t seconds, uint32_t microseconds); +void espi_reset_pin_asserted_interrupt(enum gpio_signal signal); void espi_interrupt(void); void espi_vw_interrupt(void); void espi_init(void); |