diff options
| author | Jes B. Klinke <jbk@chromium.org> | 2023-01-31 22:01:13 -0800 |
|---|---|---|
| committer | Chromeos LUCI <chromeos-scoped@luci-project-accounts.iam.gserviceaccount.com> | 2023-02-05 00:31:41 +0000 |
| commit | e6773d6f376b3aaf4d4d57e2efb7798f6ebf4618 (patch) | |
| tree | 9a4df5c11f2d4e8b84ddc2be156827a866e1aed1 /chip | |
| parent | 8b0555e515f933c105100f0c5265a7ca739224b2 (diff) | |
| download | chrome-ec-e6773d6f376b3aaf4d4d57e2efb7798f6ebf4618.tar.gz | |
chip/stm32/dfu_bootmanager_main: Add memory barrier
ARM Cortex documentation calls for an ISB instruction to be executed
immediately after modifying the stack pointer, see for instance:
https://developer.arm.com/documentation/dui0552/a/the-cortex-m3-processor/programmers-model/core-registers
It would seem that instruction prefetch will "anticipate" stack pointer
movements by counting the push and pop instructions, and that the
prefetch queue needs to be cleared if the stack pointer is manually
changed. Our particular code executes does not use the stack pointer,
but executes a register jump, which I assume will also clear the
prefetch queue. So in all likelihood, the barrier instructions is not
required here, but we could as well add it, as the documentation calls
for it.
BUG=none
TEST=make BOARD=hyperdebug, observe DFU upgrading still works
Change-Id: I2a0609670b3554a39057b429fc2e0cd1201d185c
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4216262
Reviewed-by: Brian Nemec <bnemec@google.com>
Commit-Queue: Jes Klinke <jbk@chromium.org>
Tested-by: Jes Klinke <jbk@chromium.org>
Diffstat (limited to 'chip')
| -rw-r--r-- | chip/stm32/dfu_bootmanager_main.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/chip/stm32/dfu_bootmanager_main.c b/chip/stm32/dfu_bootmanager_main.c index bad07c23b7..6fb53eee96 100644 --- a/chip/stm32/dfu_bootmanager_main.c +++ b/chip/stm32/dfu_bootmanager_main.c @@ -131,6 +131,11 @@ static void jump_to_arm_reset_vector(uint32_t addr) /* Load stack pointer */ "ldr r0, [r1, 0]\n" "msr msp, r0\n" + /* + * Memory barrier to ensure subsequent instructions uses modified + * stack pointer. + */ + "isb\n" /* Load reset vector */ "ldr r0, [r1, 4]\n" /* Jump without saving return address (would modify msp) */ |