diff options
| author | Nadim Taha <ntaha@google.com> | 2017-08-30 13:54:08 -0700 |
|---|---|---|
| committer | ChromeOS Commit Bot <chromeos-commit-bot@chromium.org> | 2017-10-24 01:53:05 +0000 |
| commit | a3bfe7b0ea2ede5a8a24232560882ae92ab75ee9 (patch) | |
| tree | 46e72a836ae339256749ff16efc878cc28ef995d /chip | |
| parent | 0adbb09a1eb7e28dc4395b1bf15d6c5dd76056f1 (diff) | |
| download | chrome-ec-a3bfe7b0ea2ede5a8a24232560882ae92ab75ee9.tar.gz | |
g: Provide a pinhold interface
This change is required to reboot the chip without bringing down the
entire platform on boards where GPIOs are wired to external active reset
signals.
BRANCH=none
BUG=none
TEST=Scoped a pin across a reset.
Change-Id: I58d93697d39a8adcdac9324d5dd9da00745aec9a
Signed-off-by: Nadim Taha <ntaha@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/644179
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
(cherry picked from commit be96cd65ed78a15c843e513cebd4345a29e6b2fa)
Reviewed-on: https://chromium-review.googlesource.com/734629
Commit-Queue: Vadim Bendebury <vbendeb@chromium.org>
Tested-by: Vadim Bendebury <vbendeb@chromium.org>
Diffstat (limited to 'chip')
| -rw-r--r-- | chip/g/system.c | 21 | ||||
| -rw-r--r-- | chip/g/system_chip.h | 16 |
2 files changed, 36 insertions, 1 deletions
diff --git a/chip/g/system.c b/chip/g/system.c index 4327a2c45b..473343e555 100644 --- a/chip/g/system.c +++ b/chip/g/system.c @@ -16,6 +16,8 @@ #include "task.h" #include "version.h" +static uint8_t pinhold_on_reset; + static void check_reset_cause(void) { uint32_t g_rstsrc = GR_PMU_RSTSRC; @@ -86,6 +88,21 @@ void system_pre_init(void) GREG32(GLOBALSEC, FLASH_REGION0_CTRL_CFG_EN) = 0; } +void system_pinhold_disengage(void) +{ + GREG32(PINMUX, HOLD) = 0; +} + +void system_pinhold_on_reset_enable(void) +{ + pinhold_on_reset = 1; +} + +void system_pinhold_on_reset_disable(void) +{ + pinhold_on_reset = 0; +} + void system_reset(int flags) { /* Disable interrupts to avoid task swaps during reboot */ @@ -106,7 +123,6 @@ void system_reset(int flags) */ GR_PMU_GLOBAL_RESET = GC_PMU_GLOBAL_RESET_KEY; #else - if (flags & SYSTEM_RESET_HARD) { /* Reset the full microcontroller */ GR_PMU_GLOBAL_RESET = GC_PMU_GLOBAL_RESET_KEY; @@ -116,6 +132,9 @@ void system_reset(int flags) * state. To accomplish this, first register a wakeup * timer and then enter lower power mode. */ + if (pinhold_on_reset) + GREG32(PINMUX, HOLD) = 1; + /* Low speed timers continue to run in low power mode. */ GREG32(TIMELS, TIMER1_CONTROL) = 0x1; /* Wait for this long. */ diff --git a/chip/g/system_chip.h b/chip/g/system_chip.h index 3f72b81611..b5b9f4cbea 100644 --- a/chip/g/system_chip.h +++ b/chip/g/system_chip.h @@ -74,4 +74,20 @@ void system_get_rollback_bits(char *value, size_t value_size); */ void system_ensure_rollback(void); +/** + * Enables holding external pins across soft chip resets. Application firmware + * is responsible for disengaging pinhold upon reset. + */ +void system_pinhold_on_reset_enable(void); + +/** + * Disables holding external pins across soft chip resets. + */ +void system_pinhold_on_reset_disable(void); + +/** + * Disengages pinhold if engaged. + */ +void system_pinhold_disengage(void); + #endif /* __CROS_EC_SYSTEM_CHIP_H */ |