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| author | Vincent Palatin <vpalatin@chromium.org> | 2018-03-01 16:45:40 +0100 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2018-03-02 06:49:06 -0800 |
| commit | f23f45e74e4c0aff7116a832556d194747997ffe (patch) | |
| tree | 348f7a5a727346f0317155b84938488c68e78a48 /chip/stm32 | |
| parent | c55f09496009249426574e1facf96a222b4e4693 (diff) | |
| download | chrome-ec-f23f45e74e4c0aff7116a832556d194747997ffe.tar.gz | |
cortex-m: enable I-cache on ARMv7-M
The ARMv7-M ISA defines standard (and optional) mechanism to manage the
CPU caches through the SCB (System Control Block) registers.
So far, only the Cortex-M7 core implements such as a mechanism (e.g. the
Cortex-M4 with caches we have are using a proprietary mechanism for the
management).
Define the functions to use the I-Cache,
and enable them on STM32H7 which is our only supported Cortex-M7 core.
The D-Cache mechanism is still To Be Done, as it involves a bit more
support in the firmware for the DMA memory areas.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=b:67081508
TEST=on ZerbleBarn, verify manually that the 'IC' bit is set in the CCR
(e.g. 'rw 0xe000ed14' returns 0x60218), and runs some CPU workload
without crash and with a speed-up.
Change-Id: I6af1021d65048b787630387f7d95797db15d069c
Reviewed-on: https://chromium-review.googlesource.com/943445
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Diffstat (limited to 'chip/stm32')
| -rw-r--r-- | chip/stm32/config-stm32h7x3.h | 3 | ||||
| -rw-r--r-- | chip/stm32/system.c | 4 |
2 files changed, 7 insertions, 0 deletions
diff --git a/chip/stm32/config-stm32h7x3.h b/chip/stm32/config-stm32h7x3.h index 72b9bd21de..4fde40b957 100644 --- a/chip/stm32/config-stm32h7x3.h +++ b/chip/stm32/config-stm32h7x3.h @@ -59,3 +59,6 @@ /* Number of IRQ vectors on the NVIC */ #define CONFIG_IRQ_COUNT 150 + +/* the Cortex-M7 core has 'standard' ARMv7-M caches */ +#define CONFIG_ARMV7M_CACHE diff --git a/chip/stm32/system.c b/chip/stm32/system.c index 4a5927d90c..d2c48cdc11 100644 --- a/chip/stm32/system.c +++ b/chip/stm32/system.c @@ -205,6 +205,10 @@ void chip_pre_init(void) uint32_t apb1fz_reg = 0; uint32_t apb2fz_reg = 0; +#ifdef CONFIG_ARMV7M_CACHE + cpu_enable_icache(); +#endif + #if defined(CHIP_FAMILY_STM32F0) apb1fz_reg = STM32_RCC_PB1_TIM2 | STM32_RCC_PB1_TIM3 | STM32_RCC_PB1_TIM6 | |