diff options
| author | Daisuke Nojiri <dnojiri@chromium.org> | 2016-04-20 14:49:56 -0700 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2016-04-25 16:49:02 -0700 |
| commit | 40c02e3ff2477df1aca7657a92905816e5a13d0c (patch) | |
| tree | 57f05231828259506bf8bfdd2c494e533715e01f /chip/stm32/uart.c | |
| parent | cb0d8108e5a5b630ec05a8d21a824cb601246bf5 (diff) | |
| download | chrome-ec-40c02e3ff2477df1aca7657a92905816e5a13d0c.tar.gz | |
Bring up STM32L476G-Eval
This patch adds initial set of files to bring up STM32L476G-Eval board.
BUG=none
BRANCH=tot
TEST=Tested console. make buildall && make tests
Change-Id: I0c0f73f31e84099746fced4214c5ed7f45468cef
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/340100
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Diffstat (limited to 'chip/stm32/uart.c')
| -rw-r--r-- | chip/stm32/uart.c | 11 |
1 files changed, 9 insertions, 2 deletions
diff --git a/chip/stm32/uart.c b/chip/stm32/uart.c index 33ef1064f0..69dc7d26d2 100644 --- a/chip/stm32/uart.c +++ b/chip/stm32/uart.c @@ -15,6 +15,7 @@ #include "task.h" #include "uart.h" #include "util.h" +#include "stm32-dma.h" /* Console USART index */ #define UARTN CONFIG_UART_CONSOLE @@ -238,7 +239,7 @@ static void uart_freq_change(void) div = DIV_ROUND_NEAREST(freq, CONFIG_UART_BAUD_RATE); #if defined(CHIP_FAMILY_STM32L) || defined(CHIP_FAMILY_STM32F0) || \ - defined(CHIP_FAMILY_STM32F3) + defined(CHIP_FAMILY_STM32F3) || defined(CHIP_FAMILY_STM32L4) if (div / 16 > 0) { /* * CPU clock is high enough to support x16 oversampling. @@ -264,15 +265,18 @@ DECLARE_HOOK(HOOK_FREQ_CHANGE, uart_freq_change, HOOK_PRIO_DEFAULT); void uart_init(void) { - /* Enable USART clock */ + /* Select clock source */ #if defined(CHIP_FAMILY_STM32F0) || defined(CHIP_FAMILY_STM32F3) #if (UARTN == 1) STM32_RCC_CFGR3 |= 0x0003; /* USART1 clock source from HSI(8MHz) */ #elif (UARTN == 2) STM32_RCC_CFGR3 |= 0x030000; /* USART2 clock source from HSI(8MHz) */ #endif /* UARTN */ +#elif defined(CHIP_FAMILY_STM32L4) + STM32_RCC_CCIPR |= (0x2 << STM32_RCC_CCIPR_USART1SEL_SHIFT); #endif /* CHIP_FAMILY_STM32F0 || CHIP_FAMILY_STM32F3 */ + /* Enable USART clock */ #if (UARTN == 1) STM32_RCC_APB2ENR |= STM32_RCC_PB2_USART1; #else @@ -316,6 +320,9 @@ void uart_init(void) #ifdef CONFIG_UART_TX_DMA /* Enable DMA transmitter */ STM32_USART_CR3(UARTN_BASE) |= STM32_USART_CR3_DMAT; +#ifdef CONFIG_UART_TX_DMA_PH + dma_select_channel(CONFIG_UART_TX_DMA_CH, CONFIG_UART_TX_DMA_PH); +#endif #else /* DMA disabled, special modes disabled, error interrupt disabled */ STM32_USART_CR3(UARTN_BASE) &= ~STM32_USART_CR3_DMAR & |