diff options
| author | Vincent Palatin <vpalatin@chromium.org> | 2014-03-03 11:10:45 -0800 |
|---|---|---|
| committer | chrome-internal-fetch <chrome-internal-fetch@google.com> | 2014-03-11 05:52:44 +0000 |
| commit | 39327cc4cd80e8f5ba30435d497c666e10cd0054 (patch) | |
| tree | 33213c418e5e72177f990ec88f1a6bc882416f10 /chip/stm32/uart.c | |
| parent | 0f73a129b42acfcad843203b602fbbcc8894c614 (diff) | |
| download | chrome-ec-39327cc4cd80e8f5ba30435d497c666e10cd0054.tar.gz | |
stm32: add support for STM32F0xx family
Add support for the STM32F0xx family of devices using a Cortex-M0 core
and slightly newer peripherals than F1xx family.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=none
TEST=run EC console on STM32F072B Discovery board.
and pass all available unit-tests on target.
Change-Id: Idaa3fcbf1c0da8a8f448c0e88e58bfd976b0a735
Reviewed-on: https://chromium-review.googlesource.com/188983
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Diffstat (limited to 'chip/stm32/uart.c')
| -rw-r--r-- | chip/stm32/uart.c | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/chip/stm32/uart.c b/chip/stm32/uart.c index 4fe1214934..e693d4ecaa 100644 --- a/chip/stm32/uart.c +++ b/chip/stm32/uart.c @@ -24,7 +24,7 @@ /* DMA channel options; assumes UART1 */ static const struct dma_option dma_tx_option = { - STM32_DMAC_USART1_TX, (void *)&STM32_USART_DR(UARTN), + STM32_DMAC_USART1_TX, (void *)&STM32_USART_TDR(UARTN), STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT }; @@ -35,7 +35,7 @@ static const struct dma_option dma_tx_option = { #ifdef CONFIG_UART_RX_DMA /* DMA channel options; assumes UART1 */ static const struct dma_option dma_rx_option = { - STM32_DMAC_USART1_RX, (void *)&STM32_USART_DR(UARTN), + STM32_DMAC_USART1_RX, (void *)&STM32_USART_RDR(UARTN), STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT | STM32_DMA_CCR_CIRC }; @@ -130,12 +130,12 @@ void uart_write_char(char c) while (!uart_tx_ready()) ; - STM32_USART_DR(UARTN) = c; + STM32_USART_TDR(UARTN) = c; } int uart_read_char(void) { - return STM32_USART_DR(UARTN); + return STM32_USART_RDR(UARTN); } void uart_disable_interrupt(void) @@ -192,7 +192,7 @@ static void uart_freq_change(void) { int div = DIV_ROUND_NEAREST(clock_get_freq(), CONFIG_UART_BAUD_RATE); -#ifdef CHIP_FAMILY_STM32L +#if defined(CHIP_FAMILY_STM32L) || defined(CHIP_FAMILY_STM32F0) if (div / 16 > 0) { /* * CPU clock is high enough to support x16 oversampling. @@ -222,7 +222,7 @@ void uart_init(void) #if (UARTN == 1) STM32_RCC_APB2ENR |= STM32_RCC_PB2_USART1; #else - STM32_RCC_APB1ENR |= STM32_RCC_PB1_USART ## UARTN; + STM32_RCC_APB1ENR |= CONCAT2(STM32_RCC_PB1_USART, UARTN); #endif /* Configure GPIOs */ |