diff options
| author | Vincent Palatin <vpalatin@chromium.org> | 2017-08-13 13:16:38 -0700 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2017-08-18 16:46:34 -0700 |
| commit | 3cbdff8b1bc3f8621a1c6801340c45b0951aee17 (patch) | |
| tree | c9585128735c06d6d6cf94ebe066ca21f2f021c8 /chip/stm32/spi_master.c | |
| parent | b6d83d456f0293f329c34c5005c578d87a7cf7cc (diff) | |
| download | chrome-ec-3cbdff8b1bc3f8621a1c6801340c45b0951aee17.tar.gz | |
stm32: add embryonic support for STM32F76x
The STM32F76x is really close to the STM32F4 family, so the most concise
implementation is just using CHIP_FAMILY_STM32F4 and adding
CHIP_VARIANT_F76X.
Tune the clock settings to 180 Mhz CPU clock as the goal is performance.
(over-drive is not implemented yet to get to 216 Mhz)
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=none
TEST=ran on nucleo-f767zi board.
'make BOARD=nucleo-f767 flash', the red LED is on and the green LED
turns on/off when pressing the user button, UART console works properly.
Change-Id: I1f67df3aec874c965c81188df46c72de210728d9
Reviewed-on: https://chromium-review.googlesource.com/612750
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
Diffstat (limited to 'chip/stm32/spi_master.c')
| -rw-r--r-- | chip/stm32/spi_master.c | 16 |
1 files changed, 13 insertions, 3 deletions
diff --git a/chip/stm32/spi_master.c b/chip/stm32/spi_master.c index 353dac3085..c0697be736 100644 --- a/chip/stm32/spi_master.c +++ b/chip/stm32/spi_master.c @@ -16,13 +16,21 @@ #include "timer.h" #include "util.h" +#if defined(CHIP_VARIANT_STM32F373) || \ + defined(CHIP_FAMILY_STM32L4) || \ + defined(CHIP_VARIANT_STM32F76X) +#define HAS_SPI3 +#else +#undef HAS_SPI3 +#endif + /* The second (and third if available) SPI port are used as master */ static stm32_spi_regs_t *SPI_REGS[] = { #ifdef CONFIG_STM32_SPI1_MASTER STM32_SPI1_REGS, #endif STM32_SPI2_REGS, -#if defined(CHIP_VARIANT_STM32F373) || defined(CHIP_FAMILY_STM32L4) +#ifdef HAS_SPI3 STM32_SPI3_REGS, #endif }; @@ -62,10 +70,11 @@ static const struct dma_option dma_tx_option[] = { STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT | F4_CHANNEL(STM32_SPI2_TX_REQ_CH) }, -#if defined(CHIP_VARIANT_STM32F373) || defined(CHIP_FAMILY_STM32L4) +#ifdef HAS_SPI3 { STM32_DMAC_SPI3_TX, (void *)&STM32_SPI3_REGS->dr, STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT + | F4_CHANNEL(STM32_SPI3_TX_REQ_CH) }, #endif }; @@ -83,10 +92,11 @@ static const struct dma_option dma_rx_option[] = { STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT | F4_CHANNEL(STM32_SPI2_RX_REQ_CH) }, -#if defined(CHIP_VARIANT_STM32F373) || defined(CHIP_FAMILY_STM32L4) +#ifdef HAS_SPI3 { STM32_DMAC_SPI3_RX, (void *)&STM32_SPI3_REGS->dr, STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT + | F4_CHANNEL(STM32_SPI3_RX_REQ_CH) }, #endif }; |