diff options
| author | Daisuke Nojiri <dnojiri@chromium.org> | 2016-10-03 12:51:52 -0700 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2016-10-05 20:58:20 -0700 |
| commit | 3afd683d683f482f003405c721800e3ba2ccb637 (patch) | |
| tree | 0d4a7a23b273d09cbe46f49f5c41eb56ceb3db2b /chip/stm32/i2c-stm32l4.c | |
| parent | 8c22c2dcd7397cddd78e518f808212a0ac86df90 (diff) | |
| download | chrome-ec-3afd683d683f482f003405c721800e3ba2ccb637.tar.gz | |
cts: Add I2C tests for read8/16/32 and write8/16/32
This patch adds tests for i2c_read8/16/32 and i2c_write8/16/32.
BUG=chromium:653183
BRANCH=none
TEST=make buildall. Run cts.py -m i2c for 100kHz with 10k ohms
pull-up registers on SCL and SDA. TH=stm32l476g-eval DUT=nucleo-f072rb.
Change-Id: I8121b1c5dc7542da45141543e35036ef41364c38
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/393331
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Diffstat (limited to 'chip/stm32/i2c-stm32l4.c')
| -rw-r--r-- | chip/stm32/i2c-stm32l4.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/chip/stm32/i2c-stm32l4.c b/chip/stm32/i2c-stm32l4.c index 0e943767b0..bffa6cea39 100644 --- a/chip/stm32/i2c-stm32l4.c +++ b/chip/stm32/i2c-stm32l4.c @@ -26,7 +26,7 @@ /* Transmit timeout in microseconds */ #define I2C_TX_TIMEOUT_MASTER (10 * MSEC) -#ifdef CONFIG_I2C_SLAVE_ADDR +#ifdef CONFIG_HOSTCMD_I2C_SLAVE_ADDR #define I2C_SLAVE_ERROR_CODE 0xec #if (I2C_PORT_EC == STM32_I2C1_PORT) #define IRQ_SLAVE STM32_IRQ_I2C1 @@ -177,7 +177,7 @@ static void i2c_init_port(const struct i2c_port_t *p) /*****************************************************************************/ -#ifdef CONFIG_I2C_SLAVE_ADDR +#ifdef CONFIG_HOSTCMD_I2C_SLAVE_ADDR static void i2c_event_handler(int port) { @@ -451,11 +451,11 @@ static void i2c_init(void) for (i = 0; i < i2c_ports_used; i++, p++) i2c_init_port(p); -#ifdef CONFIG_I2C_SLAVE_ADDR +#ifdef CONFIG_HOSTCMD_I2C_SLAVE_ADDR STM32_I2C_CR1(I2C_PORT_EC) |= STM32_I2C_CR1_RXIE | STM32_I2C_CR1_ERRIE | STM32_I2C_CR1_ADDRIE | STM32_I2C_CR1_STOPIE | STM32_I2C_CR1_NACKIE; - STM32_I2C_OAR1(I2C_PORT_EC) = 0x8000 | CONFIG_I2C_SLAVE_ADDR; + STM32_I2C_OAR1(I2C_PORT_EC) = 0x8000 | CONFIG_HOSTCMD_I2C_SLAVE_ADDR; task_enable_irq(IRQ_SLAVE); #endif } |