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author | CHLin <CHLIN56@nuvoton.com> | 2016-10-11 17:16:27 +0800 |
---|---|---|
committer | chrome-bot <chrome-bot@chromium.org> | 2016-10-12 06:30:26 -0700 |
commit | 57ad82c27400d4e4c27fac6ec283910f64b66821 (patch) | |
tree | 765dec08c62a24ae37199e98facf274fe25c7a73 /chip/npcx | |
parent | 8ba8872d3f2d403099f58a184e03404e7b016ddf (diff) | |
download | chrome-ec-57ad82c27400d4e4c27fac6ec283910f64b66821.tar.gz |
npxc: lpc: correct setting for SCI/SMI gererated from PM module
In current FW implement, there are two ways to generate SMI/SCI:
(1) Controlled by GPIO module register.(#define CONFIG_SCI_GPIO)
(2) Controlled by PM module register.(#undef CONFIG_SCI_GPIO)
This CL fix for case(2):
In this case, these two dedicated pins(GPIOC6/GPIO76) are used
as SMI/SCI and must be enabled by pinmux. Set the related pinmux
at initial.
By default, the SMI/SCI polarity is negative. This means SMI/SCI
is inverted when writing to SMI/SCIB but not inverted when reading
from them(see Section 5.2.2, figure 61 in datasheet). It will cause
the code more complicated to implement. Disable negative polarity
at init.
Modified drivers:
1. lpc.c: set pinmux for dedicated SMI/SCI pins and disable the
negative polarity.
BUG=chrome-os-partner:34346
BRANCH=none
TEST=make buildall; try hostevent(lid switch) on Wheatley with
CONFIG_SCL_GPIO undefined.
Change-Id: Ia317e54deb6861d7189b3594bd7414b53408b933
Signed-off-by: CHLin <CHLIN56@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/396718
Commit-Ready: CH Lin <chlin56@nuvoton.com>
Tested-by: CH Lin <chlin56@nuvoton.com>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@google.com>
Reviewed-by: Mulin Chao <mlchao@nuvoton.com>
Diffstat (limited to 'chip/npcx')
-rw-r--r-- | chip/npcx/lpc.c | 34 | ||||
-rw-r--r-- | chip/npcx/registers.h | 2 |
2 files changed, 28 insertions, 8 deletions
diff --git a/chip/npcx/lpc.c b/chip/npcx/lpc.c index 0ec1c904b9..6b4a93193f 100644 --- a/chip/npcx/lpc.c +++ b/chip/npcx/lpc.c @@ -139,14 +139,14 @@ static void lpc_generate_smi(void) /* Set signal high, now that we've generated the edge */ gpio_set_level(GPIO_PCH_SMI_L, 1); #else - /* Since SMIPOL is 1, clear SCIB bit means set SCI_L to high.*/ - CLEAR_BIT(NPCX_HIPMIC(PMC_ACPI), NPCX_HIPMIC_SMIB); + /* SET SMIB bit to pull SMI_L to high.*/ + SET_BIT(NPCX_HIPMIC(PMC_ACPI), NPCX_HIPMIC_SMIB); udelay(65); /* Generate a falling edge */ - SET_BIT(NPCX_HIPMIC(PMC_ACPI), NPCX_HIPMIC_SMIB); + CLEAR_BIT(NPCX_HIPMIC(PMC_ACPI), NPCX_HIPMIC_SMIB); udelay(65); /* Set signal high */ - CLEAR_BIT(NPCX_HIPMIC(PMC_ACPI), NPCX_HIPMIC_SMIB); + SET_BIT(NPCX_HIPMIC(PMC_ACPI), NPCX_HIPMIC_SMIB); #endif if (host_events & event_mask[LPC_HOST_EVENT_SMI]) CPRINTS("smi 0x%08x", @@ -168,14 +168,14 @@ static void lpc_generate_sci(void) /* Set signal high, now that we've generated the edge */ gpio_set_level(CONFIG_SCI_GPIO, 1); #else - /* Since SCIPOL is 1, clear SCIB bit means set SCI_L to high.*/ - CLEAR_BIT(NPCX_HIPMIC(PMC_ACPI), NPCX_HIPMIC_SCIB); + /* Set SCIB bit to pull SCI_L to high.*/ + SET_BIT(NPCX_HIPMIC(PMC_ACPI), NPCX_HIPMIC_SCIB); udelay(65); /* Generate a falling edge */ - SET_BIT(NPCX_HIPMIC(PMC_ACPI), NPCX_HIPMIC_SCIB); + CLEAR_BIT(NPCX_HIPMIC(PMC_ACPI), NPCX_HIPMIC_SCIB); udelay(65); /* Set signal high */ - CLEAR_BIT(NPCX_HIPMIC(PMC_ACPI), NPCX_HIPMIC_SCIB); + SET_BIT(NPCX_HIPMIC(PMC_ACPI), NPCX_HIPMIC_SCIB); #endif if (host_events & event_mask[LPC_HOST_EVENT_SCI]) @@ -870,6 +870,16 @@ static void lpc_init(void) SET_BIT(NPCX_DEVALT(1), NPCX_DEVALT1_CLKRN_SL); #endif + /* + * Set pin-mux from GPIOs to SCL/SMI to make sure toggling SCIB/SMIB is + * valid if CONFIG_SCI_GPIO isn't defined. eSPI sends SMI/SCI through VW + * automatically by toggling them, too. It's unnecessary to set pin mux. + */ +#if !defined(CONFIG_SCI_GPIO) && !defined(CONFIG_ESPI) + SET_BIT(NPCX_DEVALT(1), NPCX_DEVALT1_EC_SCI_SL); + SET_BIT(NPCX_DEVALT(1), NPCX_DEVALT1_SMI_SL); +#endif + /* Initialize Hardware for UART Host */ #if CONFIG_UART_HOST /* Init COMx LPC UART */ @@ -944,6 +954,14 @@ static void lpc_init(void) #endif #ifndef CONFIG_SCI_GPIO + /* Disable SMI/SCI Negative Polarity */ + CLEAR_BIT(NPCX_HIPMCTL(PMC_ACPI), NPCX_HIPMCTL_SCIPOL); + CLEAR_BIT(NPCX_HIPMIC(PMC_ACPI), NPCX_HIPMIC_SMIPOL); + /* + * Allow SMI/SCI generated from PM module. + * Either hardware autimatically generates, + * or set SCIB/SMIB bit in HIPMIC register. + */ SET_BIT(NPCX_HIPMIE(PMC_ACPI), NPCX_HIPMIE_SCIE); SET_BIT(NPCX_HIPMIE(PMC_ACPI), NPCX_HIPMIE_SMIE); #endif diff --git a/chip/npcx/registers.h b/chip/npcx/registers.h index 50b36227b3..b73a183131 100644 --- a/chip/npcx/registers.h +++ b/chip/npcx/registers.h @@ -946,6 +946,7 @@ enum NPCX_PMC_PWDWN_CTL_T { /* NPCX_HIPMCTL */ #define NPCX_HIPMCTL_IBFIE 0 +#define NPCX_HIPMCTL_SCIPOL 6 /* NPCX_HIPMST */ #define NPCX_HIPMST_F0 2 /* EC_LPC_CMDR_BUSY */ @@ -956,6 +957,7 @@ enum NPCX_PMC_PWDWN_CTL_T { /* NPCX_HIPMIC */ #define NPCX_HIPMIC_SMIB 1 #define NPCX_HIPMIC_SCIB 2 +#define NPCX_HIPMIC_SMIPOL 6 /* * PM Channel enumeration |