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| author | Mulin Chao <mlchao@nuvoton.com> | 2016-02-10 22:24:20 +0800 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2016-02-10 15:45:52 -0800 |
| commit | 3d2ad2985aa16081cd6110482173d4f8d8297059 (patch) | |
| tree | 0f3df99527b8783b2ffda3570cfc0e4357074917 /chip/npcx/uart.c | |
| parent | 71a8c029824f62693c9afbade597a58337cb2632 (diff) | |
| download | chrome-ec-3d2ad2985aa16081cd6110482173d4f8d8297059.tar.gz | |
nuc: Modify divider of apb2 to 1 if it's freq isn't divisible by 1MHz
We found the deviation of ITIM32 is huge since apb2's clock isn't divisible
by 1MHz. (The default resolution of hwtimer is 1us.)
The solution is set the freq of apb2 the same as core clock. Note apb2 is
twice value of original one. It will increase power consumption slightly.
But we found the difference is acceptable no matter core clock is 15M
or 13MHz.
In this version, we also use the arrays to adjust i2c bus timing if
bus' freq is 400K or 1MHz for all source clock freqs of i2c.
Modified sources:
1. i2c.c: Support all source clock freqs of i2c for best bus timing.
2. clock.c: Set divider of apb2 if it's clock isn't divisible by 1MHz.
3. uart.c: Modified baud-rate for apb2 which is the same as core clock.
BUG=chrome-os-partner:34346
TEST=make buildall -j; test nuvoton IC specific drivers
BRANCH=none
Change-Id: I6089caaaf9aa16186d7c6acf6f5fea0682a55655
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/327120
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Diffstat (limited to 'chip/npcx/uart.c')
| -rw-r--r-- | chip/npcx/uart.c | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/chip/npcx/uart.c b/chip/npcx/uart.c index b9f06f42dc..512478b05a 100644 --- a/chip/npcx/uart.c +++ b/chip/npcx/uart.c @@ -165,18 +165,18 @@ static void uart_config(void) #elif (OSC_CLK == 40000000) NPCX_UPSR = 0x30; NPCX_UBAUD = 0x02; -#elif (OSC_CLK == 33000000) +#elif (OSC_CLK == 33000000) /* APB2 is the same as core clock */ NPCX_UPSR = 0x08; - NPCX_UBAUD = 0x08; + NPCX_UBAUD = 0x11; #elif (OSC_CLK == 24000000) NPCX_UPSR = 0x60; NPCX_UBAUD = 0x00; -#elif (OSC_CLK == 15000000) +#elif (OSC_CLK == 15000000) /* APB2 is the same as core clock */ NPCX_UPSR = 0x38; - NPCX_UBAUD = 0x00; -#elif (OSC_CLK == 13000000) + NPCX_UBAUD = 0x01; +#elif (OSC_CLK == 13000000) /* APB2 is the same as core clock */ NPCX_UPSR = 0x30; - NPCX_UBAUD = 0x00; + NPCX_UBAUD = 0x01; #else #error "Unsupported Core Clock Frequency" #endif |