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authorCHLin <CHLIN56@nuvoton.com>2018-09-20 16:03:37 +0800
committerchrome-bot <chrome-bot@chromium.org>2018-09-21 03:38:16 -0700
commitdbc6feea3ed691a9f613e04af09bd8f3a28f5335 (patch)
tree2eb7cb2e2392b3037d248b2b3306ed7df865518f /chip/npcx/system.c
parent6349b8f0dc1e7182bb78f65949ab21b2a82cd392 (diff)
downloadchrome-ec-dbc6feea3ed691a9f613e04af09bd8f3a28f5335.tar.gz
npcx: Don't clear IBBR bit via a read-modify-write sequence
In npcx5/npcx7m6g/npcx7m6f, clearing the IBBR bit in the BKUP_STS register is not hazardous because the register only implements the IBBR bit. In npcx7m6fb/npcx7m7wb, the register implements two more bits (VSBY_STS/VCC1_STS). Using read-modify-write operation to clear IBBR bit will also clear these two bits unexpected if they are set. It is fine at this time because the firmware does not rely on these two new bits for any purpose. But it will be better to change it in case these two bits are used in the future. This CL also clears VSBY_STS/VCC1_STS bit (for npcx7m6fb/npcx7m7wb) when power-on reset. BRANCH=none BUG=none TEST=No build error for make buildall; Check IBBR(VSBY_STS/VCC1_STS) are cleared at initial when power-on reset. Check warining messages are printed and IBBR bit is cleared (in function system_check_bbram_on_reset and bbram_valid). Change-Id: I6dc1f5d7f35f9d591db62d1b022ea7b8d92f5b92 Signed-off-by: CHLin <CHLIN56@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/1235733 Commit-Ready: CH Lin <chlin56@nuvoton.com> Tested-by: CH Lin <chlin56@nuvoton.com> Reviewed-by: Jonathan Brandmeyer <jbrandmeyer@chromium.org>
Diffstat (limited to 'chip/npcx/system.c')
-rw-r--r--chip/npcx/system.c9
1 files changed, 6 insertions, 3 deletions
diff --git a/chip/npcx/system.c b/chip/npcx/system.c
index a286090bd8..edfbcf455b 100644
--- a/chip/npcx/system.c
+++ b/chip/npcx/system.c
@@ -98,8 +98,11 @@ void system_check_bbram_on_reset(void)
IS_BIT_SET(NPCX_RSTCTL, NPCX_RSTCTL_VCC1_RST_STS))
CPRINTF("VBAT drop!\n");
- /* Clear IBBR bit */
- SET_BIT(NPCX_BKUP_STS, NPCX_BKUP_STS_IBBR);
+ /*
+ * npcx5/npcx7m6g/npcx7m6f - Clear IBBR bit
+ * npcx7m6fb/npcx7m7wb - Clear IBBR/VSBY_STS/VCC1_STS bit
+ */
+ NPCX_BKUP_STS = NPCX_BKUP_STS_ALL_MASK;
}
}
@@ -112,7 +115,7 @@ static int bbram_valid(enum bbram_data_index index, int bytes)
/* Check BBRAM is valid */
if (IS_BIT_SET(NPCX_BKUP_STS, NPCX_BKUP_STS_IBBR)) {
- SET_BIT(NPCX_BKUP_STS, NPCX_BKUP_STS_IBBR);
+ NPCX_BKUP_STS = (1 << NPCX_BKUP_STS_IBBR);
panic_printf("IBBR set: BBRAM corrupted!\n");
return 0;
}