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| author | CHLin <CHLin56@nuvoton.com> | 2020-07-31 18:01:09 +0800 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2020-08-19 06:56:52 +0000 |
| commit | 0e91682bdbd15b8f4ab8a4e08d39d652d26164cb (patch) | |
| tree | 7836463ca6968829444e8508a207b75b2a5e5c02 /chip/npcx/system.c | |
| parent | 5f2dde0ec319b4bf1ec863e23d545df885be71c3 (diff) | |
| download | chrome-ec-0e91682bdbd15b8f4ab8a4e08d39d652d26164cb.tar.gz | |
npcx7: introduce new chip variant npcx7m7fc
Add the following changes:
1. add CHIP_VARIANT_NPCX7M7WC in the npcx7 chip configuration files to
define what (RAM, flash, features...) are supported in npcx7m7fc.
2. add the chip id and chip revision id of npcx7m7fc
BRANCH=none
BUG=b:163910671
TEST=pass "make buildall"
TEST=with related CLs, change CHIP_VARIANT to npcx7m7fc in
board/npcx7_evb/build.mk; flash image and run on the internal testing board of
npcx7m7fc; make sure the EC can boot up; check the chip ID and chip
revision ID are correct by console command "version".
Signed-off-by: CHLin <CHLin56@nuvoton.com>
Change-Id: Ibef17148eeba71bbbb63145064a5fa398c0118dc
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2355156
Tested-by: CH Lin <chlin56@nuvoton.com>
Reviewed-by: caveh jalali <caveh@chromium.org>
Reviewed-by: Keith Short <keithshort@chromium.org>
Commit-Queue: CH Lin <chlin56@nuvoton.com>
Diffstat (limited to 'chip/npcx/system.c')
| -rw-r--r-- | chip/npcx/system.c | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/chip/npcx/system.c b/chip/npcx/system.c index 2a1407d4f8..3a1c84601f 100644 --- a/chip/npcx/system.c +++ b/chip/npcx/system.c @@ -99,7 +99,7 @@ void system_check_bbram_on_reset(void) /* * npcx5/npcx7m6g/npcx7m6f: * Clear IBBR bit - * npcx7m6fb/npcx7m6fc/npcx7m7wb/npcx7m7wc: + * npcx7m6fb/npcx7m6fc/npcx7m7fc/npcx7m7wb/npcx7m7wc: * Clear IBBR/VSBY_STS/VCC1_STS bit */ NPCX_BKUP_STS = NPCX_BKUP_STS_ALL_MASK; @@ -736,7 +736,8 @@ void system_pre_init(void) #if defined(CHIP_FAMILY_NPCX7) #if defined(CHIP_VARIANT_NPCX7M6FB) || defined(CHIP_VARIANT_NPCX7M6FC) || \ - defined(CHIP_VARIANT_NPCX7M7WB) || defined(CHIP_VARIANT_NPCX7M7WC) + defined(CHIP_VARIANT_NPCX7M7FC) || defined(CHIP_VARIANT_NPCX7M7WB) || \ + defined(CHIP_VARIANT_NPCX7M7WC) NPCX_PWDWN_CTL(NPCX_PMC_PWDWN_7) = 0xE7; #else NPCX_PWDWN_CTL(NPCX_PMC_PWDWN_7) = 0x07; @@ -847,6 +848,8 @@ const char *system_get_chip_name(void) #elif defined(CHIP_FAMILY_NPCX7) case 0x1F: return "NPCX787G"; + case 0x20: + return "NPCX797F"; case 0x21: case 0x29: return "NPCX796F"; |