diff options
| author | Peter Marheine <pmarheine@chromium.org> | 2020-03-16 16:26:07 +1100 |
|---|---|---|
| committer | Chromeos LUCI <chromeos-scoped@luci-project-accounts.iam.gserviceaccount.com> | 2022-03-28 18:17:11 +0000 |
| commit | 91f79e5855bf48bfc82d99076aee3797d15fe9f0 (patch) | |
| tree | c0fe1649b135113c9f15099c99f5373ee34c7487 /chip/npcx/system.c | |
| parent | cf96131c91213628e56ed82527b83d20177609bf (diff) | |
| download | chrome-ec-91f79e5855bf48bfc82d99076aee3797d15fe9f0.tar.gz | |
Rename Cortex-M MMFS to CFSR
Taken as as 32-bit register, ARM call the register at 0xe000ed28 CFSR;
the Configurable Fault Status Register. MMFS is the low byte of this
value, so it's misleading to refer to the whole 32-bit value as MMFS;
instead call it CFSR to make it clear that the value we store
encompasses the MMFSR, BFSR and UFSR.
BUG=b:218982018
BRANCH=None
TEST=make buildall
Change-Id: Ifd62e0a6f27a2e6ddfa509b84c389d960347ff85
Signed-off-by: Peter Marheine <pmarheine@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2104807
Reviewed-by: Keith Short <keithshort@chromium.org>
(cherry picked from commit 124b2a8654b1bca281277b581fb79daeb1bdadde)
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3457944
Diffstat (limited to 'chip/npcx/system.c')
| -rw-r--r-- | chip/npcx/system.c | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/chip/npcx/system.c b/chip/npcx/system.c index edfbcf455b..cd90390e5f 100644 --- a/chip/npcx/system.c +++ b/chip/npcx/system.c @@ -244,7 +244,7 @@ void system_set_rtc(uint32_t seconds) * * index | data * ==========|============= - * 36 | MMFS + * 36 | CFSR * 40 | HFSR * 44 | BFAR * 48 | LREG1 @@ -253,11 +253,11 @@ void system_set_rtc(uint32_t seconds) * 60 | reserved * * Above registers are chosen to be saved in case of panic because: - * 1. MMFS, HFSR and BFAR seem to provide more information about the fault. + * 1. CFSR, HFSR and BFAR seem to provide more information about the fault. * 2. LREG1, LREG3 and LREG4 store exception, reason and info in case of * software panic. */ -#define BKUP_MMFS (BBRM_DATA_INDEX_PANIC_BKUP + 0) +#define BKUP_CFSR (BBRM_DATA_INDEX_PANIC_BKUP + 0) #define BKUP_HFSR (BBRM_DATA_INDEX_PANIC_BKUP + 4) #define BKUP_BFAR (BBRM_DATA_INDEX_PANIC_BKUP + 8) #define BKUP_LREG1 (BBRM_DATA_INDEX_PANIC_BKUP + 12) @@ -273,7 +273,7 @@ void chip_panic_data_backup(void) if (!d) return; - bbram_data_write(BKUP_MMFS, d->cm.mmfs); + bbram_data_write(BKUP_CFSR, d->cm.cfsr); bbram_data_write(BKUP_HFSR, d->cm.hfsr); bbram_data_write(BKUP_BFAR, d->cm.dfsr); bbram_data_write(BKUP_LREG1, d->cm.regs[1]); @@ -287,7 +287,7 @@ static void chip_panic_data_restore(void) struct panic_data *d = PANIC_DATA_PTR; /* Ensure BBRAM is valid. */ - if (!bbram_valid(BKUP_MMFS, 4)) + if (!bbram_valid(BKUP_CFSR, 4)) return; /* Ensure Panic data in BBRAM is valid. */ @@ -301,7 +301,7 @@ static void chip_panic_data_restore(void) d->struct_version = 2; d->arch = PANIC_ARCH_CORTEX_M; - d->cm.mmfs = bbram_data_read(BKUP_MMFS); + d->cm.cfsr = bbram_data_read(BKUP_CFSR); d->cm.hfsr = bbram_data_read(BKUP_HFSR); d->cm.dfsr = bbram_data_read(BKUP_BFAR); |