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| author | CHLin <CHLIN56@nuvoton.com> | 2019-03-28 10:40:08 +0800 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2019-04-03 18:13:50 -0700 |
| commit | d388343e3b01f780fa621b3c840c2557fcc6e477 (patch) | |
| tree | 51144dbb839e43e741acb6dcdea04ddf5991fdfb /chip/npcx/system.c | |
| parent | 0cb553724da2e424065c482690a2540018f3c60a (diff) | |
| download | chrome-ec-d388343e3b01f780fa621b3c840c2557fcc6e477.tar.gz | |
npcx7: introduce npcx7m7wc chip and refine memory layout of npcx7m7wb
This CL includes the following changes:
1. add CHIP_VARIANT_NPCX7M7WC in the npcx7 chip configuration files to
define what (RAM, features...) is supported in npcx7m7wc.
2. add the chip id and chip revision id of npcx7m7wc.
3. re-organize the memory of npcx7m7wb from:
current: 320 KB code RAM + 64 KB data RAM.
to : 256 KB code RAM + 128 KB data RAM.
The reason is that the extra 64 KB RAM is excepted to store the WoV
voice data when it operates under RAM mode. Under the limitation of
current memory layout, the 64 KB voice buffer is declared as const
to force it allocated in the code section, which is strange.
This can be fixed after changing the layout.
BRANCH=none
BUG=none
TEST=pass "make buildall"
TEST=with related CLs, change CHIP_VARIANT to npcx7m7wc in
board/npcx7_evb/build.mk; flash image in the internal testing board of
npcx7m7wc; make sure the EC can boot up; check the chip ID and chip
revision ID are correct by console command "version".
TEST=build npcx7m7wb image and test it on npcx7_evb, no symptom found.
Change-Id: I7533c1f5490e151571696ac615da2d0430827a78
Signed-off-by: CHLin <CHLIN56@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/1543062
Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
Tested-by: CH Lin <chlin56@nuvoton.com>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Diffstat (limited to 'chip/npcx/system.c')
| -rw-r--r-- | chip/npcx/system.c | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/chip/npcx/system.c b/chip/npcx/system.c index 4b2f55ddb4..009dd49017 100644 --- a/chip/npcx/system.c +++ b/chip/npcx/system.c @@ -101,7 +101,7 @@ void system_check_bbram_on_reset(void) /* * npcx5/npcx7m6g/npcx7m6f: * Clear IBBR bit - * npcx7m6fb/npcx7m6fc/npcx7m7wb: + * npcx7m6fb/npcx7m6fc/npcx7m7wb/npcx7m7wc: * Clear IBBR/VSBY_STS/VCC1_STS bit */ NPCX_BKUP_STS = NPCX_BKUP_STS_ALL_MASK; @@ -702,7 +702,7 @@ void system_pre_init(void) #if defined(CHIP_FAMILY_NPCX7) #if defined(CHIP_VARIANT_NPCX7M6FB) || defined(CHIP_VARIANT_NPCX7M6FC) || \ - defined(CHIP_VARIANT_NPCX7M7WB) + defined(CHIP_VARIANT_NPCX7M7WB) || defined(CHIP_VARIANT_NPCX7M7WC) NPCX_PWDWN_CTL(NPCX_PMC_PWDWN_7) = 0xE7; #else NPCX_PWDWN_CTL(NPCX_PMC_PWDWN_7) = 0x07; @@ -817,6 +817,7 @@ const char *system_get_chip_name(void) case 0x29: return "NPCX796F"; case 0x24: + case 0x2C: return "NPCX797W"; #endif default: |