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authorVadim Bendebury <vbendeb@chromium.org>2018-01-02 15:40:00 -0800
committerchrome-bot <chrome-bot@chromium.org>2018-01-03 16:54:35 -0800
commit5789d6925777d82db30d80cd2eef62f57e5c9ca7 (patch)
tree34cf8440fd8b2b1ecaec83711bfae5097d95a76a /chip/npcx/spiflashfw/monitor_hdr.c
parent27f92a378aad37bac9f2de1a311f78012eac574b (diff)
downloadchrome-ec-5789d6925777d82db30d80cd2eef62f57e5c9ca7.tar.gz
g: simulate open drain GPIO behavior
Some upcoming designs based on the g chip require GPIOs connected to open drain circuits. Even though the chip explicitly provides only two open drain GPIOs, the desired behavior of the rest of the pins when configured as 'open drain' could be simulated by software if when 'high' is required the output is disabled instead of driving the pin value. To make sure there is no fallout from RO driving the pins, also add an explicit 'disable output' initialization in case a GPIO is configured for open drain and the initial output value is 'high'. BRANCH=cr50 BUG=none TEST=verified that Cr50 booted successfully, also confirmed that on the test board that GPIOs defined as Open Drain allow we set output to 1 only if pulled up. Change-Id: Id2daa19b992bab7fb01148b6fa7b57fd0728b33d Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/848152 Reviewed-by: Randall Spangler <rspangler@chromium.org>
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